Patents by Inventor Patrick Matthew Hanrahan

Patrick Matthew Hanrahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8269768
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: September 18, 2012
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 7969436
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: June 28, 2011
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 7952579
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: May 31, 2011
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 7375727
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: May 20, 2008
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 6768487
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: July 27, 2004
    Assignee: Nvidia Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 6480205
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is obtained through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: November 12, 2002
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan