Abstract: One embodiment of the present invention sets forth a technique for performing a computer-implemented method that controls memory access operations. A stream of graphics commands includes at least one memory barrier command. Each memory barrier command in the stream of graphics command delays memory access operations scheduled for any command specified after the memory barrier command until all memory access operations scheduled for commands specified prior to the memory barrier command have completely executed.

Abstract: One embodiment of the present invention sets forth a method for accessing texture objects stored within a texture memory. The method comprises the steps of receiving a texture bind request from an application program, wherein the texture bind request includes an object identifier that identifies a first texture object stored in the texture memory and an image identifier that identifies a first image unit, binding the first texture object to the first image unit based on the texture bind request, receiving, within a shader engine, a first shading program command from the application program for performing a first memory access operation on the first texture object, wherein the memory access operation is a store operation or atomic operation to an arbitrary location in the image, and performing, within the shader engine, the first memory access operation on the first texture object via the first image unit.

Abstract: One embodiment of the present invention sets forth a technique for performing a computer-implemented method for tessellating patches. An input block is received that defines a plurality of input patch attributes for each patch as well as instructions for processing each input patch. A plurality of threads is launched to execute the instructions to generate each vertex of a corresponding output patch based on the input patch. Reads of values written during instruction execution are synchronized so threads can read and further process the values of other threads. An output patch is then assembled from the outputs of each of the threads; and emitting the output patch for further processing.

Abstract: One embodiment of the present invention sets forth a method for storing processed data within buffer objects stored in buffer object memory from within shader engines executing on a GPU. The method comprises the steps of receiving a stream of one or more shading program commands via a graphics driver, executing, within a shader engine, at least one of the one or more shading program commands to generate processed data, determining from the stream of one or more shading program commands an address associated with a first data object stored within the buffer memory, and storing, from within the shader engine, the processed data in the first data object stored within the buffer memory.

Abstract: One embodiment of the invention is a method of accessing a bindable uniform variable bound to a buffer object that includes the steps of creating a linked program object comprising one or more shader programs, where each shader program includes instructions written in a high-level shader language, and where the linked program object includes a reference to a bindable uniform variable and indicates which shader programs use the bindable uniform variable. The method also includes determining a memory size to support the bindable uniform variable, allocating a buffer object having the memory size, binding the buffer object to the bindable uniform variable, populating the buffer object with values for the bindable uniform variable, and accessing the values of the bindable uniform with one or more of the shader programs in the linked program object.

Abstract: One embodiment of the invention is a method for accessing and updating data in a buffer object during the execution of a shader program. The method includes loading a plurality of data portions in the buffer object, initiating a first execution of a shader program that accesses a first portion of data in the buffer object, receiving a request to update the first portion of data in the buffer object; updating a version of the first portion of data in the buffer object to reflect the update, initiating a second execution of a shader program that accesses the updated version of the first portion of data in the buffer object, wherein the second execution of the shader program occurs without waiting for the execution of the first shader program to complete.

Abstract: One embodiment of the invention sets forth a method for storing graphics data in a texture array in a local memory coupled to a graphics processing unit. The method includes the steps of specifying the texture array as a target in the local memory, and loading a first block of texture maps into the texture array, wherein each texture map in the first block has a first resolution and corresponds to a different slice of the texture array. One advantage of the disclosed method is that a complete block of texture images may be loaded into a texture array using a single API call. Thus, compared to prior art systems, where a texture array must be loaded one image for one slice of the array at a time, the disclosed method increases the efficiency of using arrays of texture maps for graphics processing operations.

Abstract: Methods and systems for processing a geometry shader program developed in a high-level shading language are disclosed. Specifically, in one embodiment, after having received the geometry shader program configured to be executed by a first processing unit in a programmable execution environment, the high-level shading language instructions of the geometry shader program is converted into low-level programming language instructions. The low-level programming language instructions are then linked with the low-level programming language instructions of a domain-specific shader program, which is configured to be executed by a second processing unit also residing in the programmable execution environment. The linked instructions of the geometry shader program are directed to the first processing unit, and the linked instructions of the domain-specific shader program are directed to the second processing unit.

Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.

Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A system, method and computer program product are provided for buffering data in a computer graphics pipeline. Initially, graphics floating point data is read from a buffer in a graphics pipeline. Next, the graphics floating point data is operated upon in the graphics pipeline. Further, the graphics floating point data is stored to the buffer in the graphics pipeline.

Abstract: A system, method and computer program product are provided for branching during programmable processing utilizing a graphics application program interface in conjunction with a hardware graphics pipeline. Initially, a first instruction defined by the graphics application program interface is identified. A first operation is performed on graphics data based on the first instruction utilizing the hardware graphics pipeline. Any some point, the present technique may involve branching to an additional instruction defined by the graphics application program interface other than a subsequent sequential instruction. Next, another operation is performed on the graphics data based on the additional instruction utilizing the hardware graphics pipeline.

Abstract: Improved arrangements for antialiasing coverage computations, useable in numerous embodiments, a non-exhaustive/non-limiting listing including graphics chips, chipsets, systems, methods and software embodiments.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: Improved arrangements for antialiasing coverage computations, useable in numerous embodiments, a non-exhaustive/non-limiting listing including graphics chips, chipsets, systems, methods and software embodiments.

Abstract: Detection of delaminated features on a printed circuit board. Delamination is detected by designing a sacrificial trace which is anchored by a via at one end and connects to a feature such as a pad on the other. The sacrificial trace is fragile. Delamination of the feature causes the sacrificial trace to break, interrupting an electrical circuit which is sensed to detect the failure.

Abstract: A computer graphics system simultaneously stores graphical storage areas of variable size in a two-dimensionally addressed graphics memory. The storage areas contain data corresponding to two-dimensional graphical images such as, for example, texture maps, mip maps, bit maps, or fonts. The graphics system manages the storage areas within the graphics memory using a quadtree that indicates the current storage state thereof. Using the quadtree, a memory manager divides the graphics memory address space into a first level of quadrants of equal two-dimensional size. The size of a storage area to be placed into the memory is compared with the size of the first level quadrants. If size is equal, then the storage area is placed into one of the quadrants. Otherwise, the memory manager further subdivides the graphics memory into quadrants on one or more descending levels as necessary to store the storage area within.