Abstract: A collection of data processing algorithms which, used in concert, are suitable for use in place of a high pass filter stage in an eddy current inspection system and provide for a system optimized to inspect test pieces for elongated defects running parallel to the scan axis. The algorithms use mathematical techniques to eliminate baseline impedance offset between test pieces, correct for offset drift during a scan, and allow for system balancing using only a set of test pieces of unknown quality.

Abstract: A collection of data processing algorithms which, used in concert, are suitable for use in place of a high pass filter stage in an eddy current inspection system and provide for a system optimized to inspect test pieces for elongated defects running parallel to the scan axis. The algorithms use mathematical techniques to eliminate baseline impedance offset between test pieces, correct for offset drift during a scan, and allow for system balancing using only a set of test pieces of unknown quality.

Abstract: The network comprises a master node and a plurality of slave nodes. To configure the network, the master node transmits over the network a hailing message at any attenuated level compared to normal communication signals to be transmitted over the network. Upon receiving the hailing message at one of the slave node, a reply message is transmitted, also at an attenuated level. Receiving the reply message at the master node allows it to configure the slave node from which the reply message originated. Also disclosed are a method of managing a network so as to monitor the connections between the slave nodes, and a method of managing a network when a recovery operation is required.

Abstract: A digital video encode system, method and computer program product are described wherein a picture is divided into multiple active areas that are parallel encoded using multiple encoders. The encoders associated with adjoining active areas of the picture are configured to exchange reference data to facilitate avoiding appearance of a seam between the adjoining active areas of a subsequent picture in a sequence of pictures due to separate encoding thereof by the multiple encoders. The reference data transferred from one encoder to an adjoining encoder is an encoded and decoded section of the picture and is used by the adjoining encoder as an expanded reference area for motion estimation when encoding the subsequent picture.

Abstract: System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted.

Abstract: Method and apparatus for detecting and correcting error in an uncompressed digital video image data stream. The method and apparatus identify error or partial picture scenarios. Each of the possible error or partial picture scenarios is identified in a Partial Picture Repair Unit, which causes error processing of the uncompressed video input stream, resulting in the creation of a repaired data stream on the repaired pixel bus. The repair begins upon detection of an erroneous picture, field, or line. Processing for that picture, field or line is stopped upon detection of an error in the synchronization signals, and processing is resumed when the end of line, end of field, or end of picture indicator is detected.

Abstract: A filter for downsampling input video having a first chrominance sampling to a second chrominance sampling. The input video has a Bitstream of data representing a sequence of picture frames, where each picture frame has a plurality of video lines. The filter has a means for choosing a downsampling mode from a list of available downsampling modes for the downsampling of the first chrominance sampling. The filter also has a means for dividing each picture frame into video line sets according to predetermined criteria for the particular downsampling mode chosen, where each video line set has at least two video lines. A means for assigning default downsampling coefficients for each of the video lines in the video line sets based upon the downsampling mode chosen is also provided in the filter. Lastly, the filter has a means for downsampling each video line set to a single video line having the second chrominance sampling.

Abstract: More than 2 power N external conditions are determined by a circuit package. Connections are made from N inputs to either a first or second contact at either a first or second logic state respectively or to digital outputs. The outputs may be sequentially placed at either the first or second logic state. By recording an indication signal from the inputs an electronic circuit is adapted to determine more than 2 power N conditions.

Abstract: Method and apparatus for detecting and correcting error in an uncompressed digital video image data stream. The method and apparatus identify error or partial picture scenarios. Each of the possible error or partial picture scenarios is identified in a Partial Picture Repair Unit, which causes error processing of the uncompressed video input stream, resulting in the creation of a repaired data stream on the repaired pixel bus. The repair begins upon detection of an erroneous picture, field, or line. Processing for that picture, field or line is stopped upon detection of an error in the synchronization signals, and processing is resumed when the end of line, end of field, or end of picture indicator is detected.

Abstract: Disclosed is an integrated microprocessor chip. The chip includes a digital video decoder Inverse Discrete Cosine Transform element and an on chip Read Only Memory. The on chip Read Only Memory includes (a) a shift register latch for receiving data from off chip pull-up resistors, (b) a register for storing data, (c) a selector and a decoder for selecting memory cells to be read from the register, and (d) a Read Only Memory data output.

Abstract: Disclosed is a circuit for determining whether an incoming signal is a speech signal or a data signal. In the preferred embodiment, means for separating the incoming signal into a low frequency component and a high frequency component are provided. The low frequency component consists of frequencies below a specified frequency, namely 1000 Hz. and the high frequency component consists of frequencies above 1000 Hz. Means are also provided for the comparison of the energy level of the high frequency components with a multiple of the energy level of the low frequency components. Also, means are provided for comparing a multiple of the energy level of the low frequency components with a maximum threshold and for comparing the energy level of the high frequency components with a minimum threshold. Further, means are provided for detecting whether the incoming signal has a slope.

Abstract: Disclosed is an automatic gain control circuit for a communications system, such as a time assignment speech interpolation system, which equalizes the loss in each of a plurality of transmission facilities by providing a symbol generator at a remote location for generating a test signal of predetermined amplitude. At a near location, the received test signal is applied to a controlled gain circuit for each facility, which is under the control of a central microprocessor provided with a reference signal for comparing the received test signal against the reference signal. The gain of the controlled gain circuit may be increased or decreased in accordance with the comparison of the received test signal with the reference signal. In one embodiment, the sum of the digital samples of the received test signal is compared against a reference value stored in a digital memory. In the preferred embodiment the stored reference value comprises a low and a high value which define an acceptable amplitude range therebetween.

Abstract: Disclosed is an echo suppressor circuit which provides a variable loss in a speaker's transmit path, which loss is a function of the relative speaker volumes. The loss provided in the path of a particular speaker is relative to the volume of the speech emanating from each speaker. In one embodiment, the amplitude of the incoming signal is reduced by an amount which is a function of the ratio of the amplitude of the incoming signal to the amplitude of the outgoing signal. Because loss is introduced into a distant speaker's transmit path rather than into his return path, it is possible for a near speaker to break into a conversation before the distant speaker has concluded. Further, since the loss provided is a function of the relative volumes of both speakers with respect to one another, the total loss introduced into the system is minimized.