Patents by Inventor Patrick Variot

Patrick Variot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6110815
    Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: August 29, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 6088914
    Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: July 18, 2000
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 6054767
    Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 25, 2000
    Assignee: LSI Logic Corp.
    Inventors: Chok J. Chia, Seng-Sooi Lim, Patrick Variot
  • Patent number: 5989937
    Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: November 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5981311
    Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Patrick Variot
  • Patent number: 5933710
    Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot
  • Patent number: 5901437
    Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5869889
    Abstract: An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: February 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 5841198
    Abstract: A ball grid array package utilizes solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface, thus preventing molten solder from being squashed and flowing to adjacent ball contacts.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: November 24, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 5789811
    Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: August 4, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot
  • Patent number: 5745986
    Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit on a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: May 5, 1998
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5692296
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: December 2, 1997
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5570272
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: October 29, 1996
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5563446
    Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.
    Type: Grant
    Filed: January 25, 1994
    Date of Patent: October 8, 1996
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot
  • Patent number: 5557150
    Abstract: A technique for providing partially and fully overmolded semiconductor packages is described which prevents delamination (detachment) of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming it into rivet-like anchors on the opposite side of the substrate. Various shapes of rivet-like anchors are described. Different embodiments provide for the formation of molded standoffs and locating pins integral to the anchor structures.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia
  • Patent number: 5527743
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: June 18, 1996
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5435482
    Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: July 25, 1995
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5420752
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are nonfunctional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: May 30, 1995
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5386144
    Abstract: A heat sink (44-48) is detachably mechanically connected to an electronic component package (10) by means of a pair of mutually spaced and parallel spring rods (16, 18) that are fixed to the electronic component package and span a recess (14) formed in a surface of the package. The heat sink is formed with a projecting latching member (50) having a short shank (52) on the end of which is formed a laterally outwardly extending flange (60). The flange has shoulders (62) that slope outwardly and away from the heat sink body and distal ends on which are formed cam surfaces (66) that slope inwardly away from the heat sink body. The latching member (50) of the heat sink is pressed into the electronic component package recess between the resilient rods (16, 18) to force the rods apart and to pass the outer most ends (64) of the flange this causes the rods to contact the flange shoulders (62) in a slightly outwardly bowed position of the rods.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: January 31, 1995
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Qwai H. Low, Maniam Alagaratnam, Teresa Dalao