Abstract: Continuous time pipeline, level-crossing (LC), analog-to-digital converters (ADCs) use a plurality of stages from a first stage to a last stage. Each stage has an array of comparators that are provided with an array of reference voltage levels. Each stage is configured to detect level crossings of increasing fineness compared to the preceding stage such that the accuracy of a digitized representation of an input signal can be increased by adding stages as well as increasing the number of comparators in each stage. The voltage error in the digitized representation of the signal that remains after each stage provides the input to the subsequent stage. The continuous time pipeline LC ADCs are also applied to analog signal processing and software defined radios.

Abstract: A computing architecture using at least one state machine to apply security rules to an execution pipeline of a computing device (e.g., microprocessor) and generate error notifications (e.g., hardware exceptions) when content within the execution pipeline impacts computer security.

Abstract: A microprocessor computer system for secure/high assurance/safety critical computing includes a hardware subsystem having a plurality of cache controller and cache bank modules including cache bank and memory cell hardware permission bits for managing and controlling access to system resources. A computer security framework subsystem includes a hierarchy of access layers comprising top layers and lower layers. The permission bits provide hardware level computer security primitives for a computer operating system. The top layers are completely trusted and the lower layers are moderately trusted to completely untrusted. The top layers include a trusted operating system layer that executes management and control of the system resources and permission bits. The permission bits define limits for a hardware execution security mechanism for less trusted to completely untrusted software.

Abstract: A microprocessor computer system for secure/high assurance/safety critical computing includes a hardware subsystem having a plurality of cache controller and cache bank modules including cache bank and memory cell hardware permission bits for managing and controlling access to system resources. A computer security framework subsystem includes a hierarchy of access layers comprising top layers and lower layers. The permission bits provide hardware level computer security primitives for a computer operating system. The top layers are completely trusted and the lower layers are moderately trusted to completely untrusted. The top layers include a trusted operating system layer that executes management and control of the system resources and permission bits. The permission bits define limits for a hardware execution security mechanism for less trusted to completely untrusted software.

Abstract: A VLIW processor is provided with an architecture which includes fetching and executing circuitry which when combined with operation, compare, branch (OCB) instructions realizes no processing branch penalties. The OCB instructions are provided with two direct branch fields or with two indirect branch fields.

Abstract: An Operation, Compare, Branch (OCB) VLIW instruction word has a memory address, a respective operation code, a respective comparison and branch code; and at least two respective branch pointers. A plurality of OCB VLIW instructions are contained in memory. The branch pointers of a given instruction word connect to a memory address determined by a comparison analysis. The branch pointers form a linked list structure connecting the OCB instructions together, thus no program counter is required. The OCB instructions can be scrambled to realize a branch obfuscated program with built in software protections in that software protection mechanisms can be placed in the lengths and positions of the pointers. The processor architecture allows multiple branching without branch penalties. Other prior art obfuscation techniques may be applied to software programs for the OCB processor.

Abstract: The Continuous Aimpoint Tracking System is comprised of a position detection device (PDD) and a laser pointing device (LPD) that projects an infrared crosshair onto the PDD. The PDD is coupled to a computer and comprises a multitude of photodiodes and associated circuits, the photodiodes being evenly spaced and arranged to form a frame that can be mounted on the computer so as to surround the computer video display. When a “shot” is fired from the LPD, the crosshair projection is interrupted briefly. The PDD determines the position of the four crosshair intersections and reports them to the computer which, in response, generates the video signals that form the resolved aimpoint on the screen, matching the LPD aimpoint to the video image. Further, the tracking system determines the rotation of the LPD over a range of at least 10 degrees clockwise or counter-clockwise.

Abstract: The Continuous Aimpoint Tracking System is comprised of a position detection device (PDD) and a laser pointing device (LPD) that projects an infrared crosshair onto the PDD. The PDD is coupled to a computer and comprises a multitude of photodiodes and associated circuits, the photodiodes being evenly spaced and arranged to form a frame that can be mounted on the computer so as to surround the computer video display. When a “shot” is fired from the LPD, the crosshair projection is interrupted briefly. The PDD determines the position of the four crosshair intersections and reports them to the computer which, in response, generates the video signals that form the resolved aimpoint on the screen, matching the LPD aimpoint to the video image. Further, the tracking system determines the rotation of the LPD over a range of at least 10 degrees clockwise or counter-clockwise.