Abstract: An architecture of an RFID system that facilitates the accessing of RFID tag data within an RFID environment. The architecture includes a plurality of RFID readers, each reader being operative to transmit a first RF signal for scanning at least one RFID tag disposed within an RF coverage region associated with the reader, and to receive at least one second RF signal including tag data in response to the scanning of the tag. The architecture further includes at least one host computer operative to execute at least one client application, and at least one controller/processor communicably coupled to the plurality of readers and the at least one host computer. The controller/processor is operative to control operation of the plurality of readers, to process the tag data received by the plurality of readers, and to provide the processed tag data to the at least one host computer for use by the at least one client application executing thereon.

Abstract: A system is described where delay and bandwidth guarantees are implemented with a crossbar switch. A rate controller is provided as a front-end to a crossbar switch with an arbiter running a work-conserving arbitration algorithm. The system provides bandwidth and delay guarantees to all properly behaving flows independently of improperly behaving flows.

Abstract: A technique for updating a content addressable memory is disclosed. In one exemplary embodiment, wherein the content addressable memory has a plurality of entries, and wherein each of the plurality of entries has a prefix field, a prefix length field, and an associated index identifier, the technique is realized by determining a first index identifier associated with a first of the plurality of entries, wherein the first entry has a first prefix with a first prefix length that is greater than a third prefix length of a third prefix to be added to the content addressable memory. A second index identifier associated with a second of the plurality of entries is also determined, wherein the second entry has a second prefix with a second prefix length that is less than the third prefix length of the third prefix to be added to the content addressable memory. Based upon the first index identifier and the second index identifier, a third index identifier is determined.

Abstract: A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch.

Abstract: A technique for updating a content addressable memory is disclosed. In one exemplary embodiment, wherein the content addressable memory has a plurality of entries, and wherein each of the plurality of entries has a prefix field, a prefix length field, and an associated index identifier, the technique is realized by determining a first index identifier associated with a first of the plurality of entries, wherein the first entry has a first prefix with a first prefix length that is greater than a third prefix length of a third prefix to be added to the content addressable memory. A second index identifier associated with a second of the plurality of entries is also determined, wherein the second entry has a second prefix with a second prefix length that is less than the third prefix length of the third prefix to be added to the content addressable memory. Based upon the first index identifier and the second index identifier, a third index identifier is determined.

Abstract: A technique for updating a content addressable memory is disclosed. In one exemplary embodiment, wherein the content addressable memory has a plurality of entries, and wherein each of the plurality of entries has a prefix field, a prefix length field, and an associated index identifier, the technique is realized by determining a first set of index identifiers, wherein each index identifier in the first set of index identifiers is associated with a respective entry in a first set of the plurality of entries, and wherein each entry in the first set of entries has a respective prefix with a respective prefix length that is greater than a third prefix length of a third prefix to be added to the content addressable memory. A second set of index identifiers is analogously determined. Based upon the first set of index identifiers and the second set of index identifiers, a third index identifier is determined.

Abstract: A technique for updating a content addressable memory is disclosed. In one exemplary embodiment, wherein the content addressable memory has a plurality of entries, and wherein each of the plurality of entries has a prefix field, a prefix length field, and an associated index identifier, the technique is realized by determining a first set of index identifiers, wherein each index identifier in the first set of index identifiers is associated with a respective entry in a first set of the plurality of entries, and wherein each entry in the first set of entries has a respective prefix with a respective prefix length that is greater than a third prefix length of a third prefix to be added to the content addressable memory. A second set of index identifiers is analogously determined. Based upon the first set of index identifiers and the second set of index identifiers, a third index identifier is determined.

Abstract: A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch.

Abstract: An arbitration scheme for providing deterministic bandwidth and delay guarantees in an input-buffered crossbar switch with speedup S is presented. Within the framework of a crossbar architecture having a plurality of input channels and output channels, the arbitration scheme determines the sequence of fixed-size packet (or cell) transmissions between the inputs channels and outputs channels satisfying the constraint that only one cell can leave an input channel and enter an output channel per phase in such a way that the arbitration delay is bounded for each cell awaiting transmission at the input channel. If the fixed-sized packets result from fragmentation of variable size packets, the scheduling and arbitration scheme determines deterministic delay guarantees to the initial variable size packets (re-assembled at the output channel) as well.