Patents by Inventor Pau CABRE

Pau CABRE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, apparatus and system for modular on-die coherent interconnect for packetized communication
    Patent number: 9921989
    Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Krishnakumar Ganapathy, Yen-Cheng Liu, Antonio Juan, Steven R. Page, Jeffrey D. Chamberlain, Pau Cabre, Bahaa Fahim, Gunnar Gaubatz
  • METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT
    Publication number: 20160012010
    Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.
    Type: Application
    Filed: May 8, 2015
    Publication date: January 14, 2016
    Inventors: Krishnakumar GANAPATHY, Yen-Cheng LIU, Antonio JUAN, Steven R. PAGE, Jeffrey D. CHAMBERLAIN, Pau CABRE, Bahaa FAHIM, Gunnar GAUBATZ
  • RELIABILITY ENHANCEMENTS FOR HIGH SPEED MEMORY - PARITY PROTECTION ON COMMAND/ADDRESS AND ECC PROTECTION ON DATA
    Publication number: 20140089755
    Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Shveta KANTAMSETTI, Antonio JUAN, Hoi M. NG, Warren R. MORROW, Isaac HERNANDEZ, Pau CABRE, Thomas S. NG, Tsun Ho LIU, Rongchun SUN, Jessica LEUNG, Mohamedsha MALIKANSARI, Henry STRACOVSKY