Abstract: A unique interface adapter is described which includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from a data signal transmitted on two forward data signals. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether an output register or a data direction register is to be loaded in response to the read/write signal with the data portion of the data signal. The binary states of the data direction register determine which ones of the interface signals are to be output signals, and enable corresponding output register signals to be applied to the interface signals by way of transmission gates.