Patents by Inventor Paul A. LaBerge

Paul A. LaBerge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS
    Publication number: 20080211557
    Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.
    Type: Application
    Filed: May 16, 2008
    Publication date: September 4, 2008
    Applicant: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Method and Apparatus for Data Transfer
    Publication number: 20080155141
    Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.
    Type: Application
    Filed: March 4, 2008
    Publication date: June 26, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Paul A. LaBerge
  • System and method for controlling timing of output signals
    Patent number: 7379382
    Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Method and apparatus for data transfer
    Patent number: 7356723
    Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: April 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Paul A LaBerge
  • System and method for testing integrated circuit timing margins
    Patent number: 7355387
    Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: April 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • System and method for testing integrated circuit timing margins
    Publication number: 20080061766
    Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.
    Type: Application
    Filed: November 9, 2007
    Publication date: March 13, 2008
    Inventor: Paul LaBerge
  • Method and apparatus for supplementary command bus
    Patent number: 7339838
    Abstract: An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Micron Technology
    Inventor: Paul A LaBerge
  • Integrated testing apparatus, systems, and methods
    Publication number: 20080052585
    Abstract: Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 28, 2008
    Inventors: Paul A. LaBerge, Jeffrey J. Rooney, Charles K. Snodgrass
  • System and method for read synchronization of memory modules
    Patent number: 7330992
    Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Paul LaBerge
  • System and method for testing write strobe timing margins in memory devices
    Patent number: 7284169
    Abstract: Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Keith J. Lunzer
  • Modified persistent auto precharge command protocol system and method for memory devices
    Patent number: 7277996
    Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Jeffery W. Janzen
  • Dynamic command and/or address mirroring system and method for memory modules
    Publication number: 20070143553
    Abstract: A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.
    Type: Application
    Filed: February 13, 2007
    Publication date: June 21, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Paul LaBerge
  • System and method for testing write strobe timing margins in memory devices
    Publication number: 20070136627
    Abstract: Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 14, 2007
    Inventors: Paul LaBerge, Keith Lunzer
  • System and method for testing integrated circuit timing margins
    Publication number: 20070132443
    Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 14, 2007
    Inventor: Paul LaBerge
  • Method for modifying an integrated circuit
    Patent number: 7222325
    Abstract: An application specific integrated circuit has at least one standard cell, integrated circuit connection circuitry connected to the at least one standard cell and at least one programmable circuit that is connected or selectively connectable to the integrated circuit connection circuitry. The selected connection is made by metal mask changes if and when it is desirable to change the logic of the application specific circuit. The programmable circuit is a general-purpose logic block and may be reprogrammed to effect design changes.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 22, 2007
    Inventor: Paul A. LaBerge
  • System and method for controlling timing of output signals
    Publication number: 20070097778
    Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventor: Paul LaBerge
  • System and method for varying test signal durations and assert times for testing memory devices
    Publication number: 20070083800
    Abstract: A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in each of its branches, thereby producing respective first and second delayed clock signals. A test signal generator generates a plurality of test signals that may simulate memory command or address signal. A multiplexer couples the test signals to first and second inputs of a transmitter in a normal test mode but to only the first input in a special test mode. The transmitter outputs the signal applied to its first input responsive to the first delayed clock signal and it outputs the signal applied to its second input responsive to the second delayed clock signal.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 12, 2007
    Inventor: Paul LaBerge
  • Memory devices with buffered command address bus
    Publication number: 20070079049
    Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.
    Type: Application
    Filed: November 3, 2006
    Publication date: April 5, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Paul LaBerge
  • Testing system and method allowing adjustment of signal transmit timing
    Publication number: 20070046309
    Abstract: A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer into which the memory device signal is latched is determined by a write pointer, which is incremented by the first clock signal. The outputs of the buffers are applied to a multiplexer, which is controlled by a read pointer to couple a memory device signal from one of the buffers to the memory device. The read pointer is incremented by a second clock signal having a timing that is adjustable and may be different from the second clock signal used to increment the read pointer in a clock domain crossing circuit for a different memory device signal.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 1, 2007
    Inventor: Paul LaBerge
  • Dynamic command and/or address mirroring system and method for memory modules
    Patent number: 7181584
    Abstract: A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge