Patents by Inventor Paul A Lauro

Paul A Lauro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170194449
    Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20170194456
    Abstract: According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20170148635
    Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Ibrahim Alhomoudi
  • Patent number: 9578736
    Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 21, 2017
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9570295
    Abstract: Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9564335
    Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 7, 2017
    Assignees: International Business Machines Corporation, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Ibrahim Alhomoudi
  • Patent number: 9502278
    Abstract: A substrate holder assembly for use in a controlled spalling process is provided. The substrate holder assembly includes a base structure having a surface in which a base substrate or other work piece can be placed thereupon. A framing element is located above and spaced apart from the surface of the base structure. The framing element has a window which exposes an upper surface of the base substrate and defines an area of the upper surface of the base substrate in which another material can be applied thereto. A support structure containing at least one mechanical securing element is located on the framing element. The support structure mechanically constrains the base substrate within the substrate holder assembly. Each mechanical securing element contacts at least one surface of the support structure and, optionally, one surface of the base substrate.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9502609
    Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20160284954
    Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20160284928
    Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.
    Type: Application
    Filed: June 19, 2015
    Publication date: September 29, 2016
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9455180
    Abstract: In one example, a method for fabricating a device includes patterning a substrate with a set of features forming a portion of the device, depositing a first photoresist layer on the substrate by a first deposition process, depositing a second photoresist layer on the first photoresist layer by a second deposition process, and inducing spalling of the features from the substrate, after depositing the second photoresist layer.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20160183362
    Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.
    Type: Application
    Filed: October 7, 2015
    Publication date: June 23, 2016
    Inventors: Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20160183358
    Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Publication number: 20160163553
    Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 9, 2016
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Ibrahim Alhomoudi
  • Publication number: 20160118358
    Abstract: Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Inventors: Bing Dang, Michael A. Gaynes, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 9308714
    Abstract: A compliant material is formed between a base substrate and a support structure prior to performing a controlled spalling process. By positioning the compliant material between the base substrate and the support structure, the localized effects of surface perturbations (particles, wafer artifacts, etc.) on spalling mode fracture can be reduced. The method of the present disclosure thus leads to improved surface quality of the spalled material layer and the remaining base substrate. Moreover, the method of the present disclosure can reduce the density of cleaving artifacts.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9295166
    Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 9273408
    Abstract: Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bing Dang, Michael A. Gaynes, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 9275867
    Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 1, 2016
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Ibrahim Alhomoudi
  • Patent number: 9263363
    Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gareth Hougham, Paul A. Lauro, Brian R. Sundlof, Jeffrey D. Gelorme