Patents by Inventor Paul ARMAND
Paul ARMAND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11926504Abstract: A system and a method of implementing and using a preset elevator call using an elevator system and a mobile device are provided. The method includes generating the preset elevator call that includes programmed conditions that include a destination floor, storing the preset elevator call in a user profile on the mobile device and at least one corresponding triggering condition, retrieving the preset elevator call based on detecting the corresponding triggering condition, and executing the retrieved preset elevator call.Type: GrantFiled: April 6, 2016Date of Patent: March 12, 2024Assignee: OTIS ELEVATOR COMPANYInventors: Lucien Wedzikowski, Adam Kuenzi, Bradley Armand Scoville, Kelly Martin Dubois, Ashley Chapman, Paul A. Simcik, Eric C. Peterson
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Publication number: 20240055376Abstract: A method of soldering a semiconductor chip to a chip carrier includes arranging a solder deposit including solder and solder flux between a contact portion of the carrier and a contact portion of a chip pad arranged at a surface of the semiconductor chip. Arranging a dielectric layer at the surface of the semiconductor chip. The dielectric layer includes an opening within which the contact portion of the chip pad is exposed. The dielectric layer further includes arranging a solder flux outgassing trench separate from the opening and intersecting with the solder deposit. The method further includes melting the solder deposit which causes liquid solder to be moved over the solder flux outgassing trench for extraction of flux gas.Type: ApplicationFiled: October 10, 2023Publication date: February 15, 2024Inventors: Michael Stadler, Paul Armand Asentista Calo
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Patent number: 11830835Abstract: A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.Type: GrantFiled: August 17, 2021Date of Patent: November 28, 2023Assignee: Infineon Technologies AGInventors: Michael Stadler, Paul Armand Asentista Calo
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Publication number: 20230230903Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.Type: ApplicationFiled: December 21, 2022Publication date: July 20, 2023Applicant: Infineon Technologies AGInventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
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Publication number: 20230095545Abstract: A semiconductor package includes a leadframe including a diepad and a first row of leads, wherein at least one lead of the first row of leads is physically separated from the diepad by a gap. The semiconductor package further includes a semiconductor component arranged on the leadframe. The semiconductor package further includes an encapsulation material encapsulating the leadframe and the semiconductor component, wherein the encapsulation material includes a bottom surface arranged at a bottom surface of the semiconductor package, a top surface and a side surface extending from the bottom surface to the top surface. A side surface of at least one lead of the first row of leads is flush with the side surface of the encapsulation material. The flush side surface of the at least one lead is covered by an electroplated metal coating.Type: ApplicationFiled: September 22, 2022Publication date: March 30, 2023Inventors: Paul Armand Calo, Thomas Bemmerl, Joo Ming Goa, Edward Myers, Wee Boon Tay, Stefan Macheiner, Markus Dinkel, Andreas Piller
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Publication number: 20220375883Abstract: A method for fabricating an electrical or electronic device package includes providing a first plateable encapsulation layer; activating first selective areas on a main surface of the first plateable encapsulation layer; forming a first metallization layer by electrolytic or electroless plating on the first activated areas; and fabricating a passive electrical component on the basis of the first metallization layer.Type: ApplicationFiled: May 11, 2022Publication date: November 24, 2022Inventors: Kok Yau Chua, Paul Armand Asentista Calo, Chee Hong Lee
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Publication number: 20220278085Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.Type: ApplicationFiled: February 22, 2022Publication date: September 1, 2022Applicant: Infineon Technologies AGInventors: Chau Fatt CHIANG, Paul Armand Asentista CALO, Chan Lam CHA, Kok Yau CHUA, Chee Hong LEE, Swee Kah LEE, Theng Chao LONG, Jayaganasan NARAYANASAMY, Khay Chwan Andrew SAW
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Patent number: 11355429Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.Type: GrantFiled: January 28, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Paul Armand Asentista Calo, Tek Keong Gan, Ser Yee Keh, Tien Heng Lem, Fong Lim, Michael Stadler, Mei Qi Tay
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Publication number: 20220122906Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.Type: ApplicationFiled: September 27, 2021Publication date: April 21, 2022Applicant: Infineon Technologies AGInventors: Sergey YUFEREV, Paul Armand Asentista CALO, Theng Chao LONG, Josef MAERZ, Chee Yang NG, Petteri PALM, Wae Chet YONG
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Patent number: 11274984Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: GrantFiled: June 2, 2020Date of Patent: March 15, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20220068851Abstract: A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.Type: ApplicationFiled: August 17, 2021Publication date: March 3, 2022Inventors: Michael Stadler, Paul Armand Asentista Calo
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Patent number: 11211356Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.Type: GrantFiled: August 12, 2020Date of Patent: December 28, 2021Assignee: Infineon Technologies AGInventors: Wee Aun Jason Lim, Paul Armand Asentista Calo, Ting Soon Chin, Chooi Mei Chong, Sanjay Kumar Murugan, Ying Pok Sam, Chee Voon Tan
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Publication number: 20210233839Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Paul Armand Asentista Calo, Tek Keong Gan, Ser Yee Keh, Tien Heng Lem, Fong Lim, Michael Stadler, Mei Qi Tay
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Patent number: 10998691Abstract: A method and system for adjusting the profile of a laser wavefront formed by at least a laser beam to a desired laser wavefront profile, the laser beam or beams presenting random phases and intensities, comprises a mixing module, configured to generate, from interference phenomena among the laser beam or beams, a laser field, a second intensity measuring module configured to measure the mixed intensities of the laser field portions, a calculation unit configured to calculate one or several phase correction values of the phase of the laser beam or the phases of laser beams, from the intensities of the laser beams, the mixed intensities and one or several predetermined target phases, and a phase adjustment module configured to apply the phase correction value or values obtained from the calculation unit to the laser beam phases.Type: GrantFiled: January 17, 2019Date of Patent: May 4, 2021Assignees: COMPAGNIE INDUSTRIELLE DES LASERS CILAS, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITÉ DE LIMOGESInventors: Paul Armand, Jérémy Saucourt, Vincent Kermene, Agnès Desfarges-Berthelemot, Joël Benoist, Alain Barthelemy, Julien Leval
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Publication number: 20210057375Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.Type: ApplicationFiled: August 12, 2020Publication date: February 25, 2021Inventors: Wee Aun Jason Lim, Paul Armand Asentista Calo, Ting Soon Chin, Chooi Mei Chong, Sanjay Kumar Murugan, Ying Pok Sam, Chee Voon Tan
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Publication number: 20210025774Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: ApplicationFiled: June 2, 2020Publication date: January 28, 2021Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20200051898Abstract: In an embodiment, a leadframe includes a first electrically conductive part and a second electrically conductive part, each having an outer surface arranged to provide substantially coplanar outer contact areas having a footprint and an inner surface opposing the outer surface, the first part being spaced apart from the second part by a gap, a first recess arranged in the inner surface of the first part, a second recess arranged in the inner surface of the second part, and a first electrically conductive insert that is arranged in, and extends between, the first recess and the second recess and bridges the gap between the first part and the second part.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Kok Yau Chua, Josef Hoeglauer, Swee Kah Lee, Khay Chwan Saw
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Publication number: 20190221992Abstract: A method and system for adjusting the profile of a laser wavefront formed by at least a laser beam to a desired laser wavefront profile, the laser beam or beams presenting random phases and intensities, comprises a mixing module, configured to generate, from interference phenomena among the laser beam or beams, a laser field, a second intensity measuring module configured to measure the mixed intensities of the laser field portions, a calculation unit configured to calculate one or several phase correction values of the phase of the laser beam or the phases of laser beams, from the intensities of the laser beams, the mixed intensities and one or several predetermined target phases, and a phase adjustment module configured to apply the phase correction value or values obtained from the calculation unit to the laser beam phases.Type: ApplicationFiled: January 17, 2019Publication date: July 18, 2019Applicants: COMPAGNIE INDUSTRIELLE DES LASERS CILAS, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITÉ DE LIMOGESInventors: Paul Armand, Jérémy Saucourt, Vincent Kermene, Agnès Desfarges-Berthelemot, Joël Benoist, Alain Barthelemy, Julien Leval
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Publication number: 20190082619Abstract: An aeroponic system for supporting efficient low-resource-usage plant growth comprises a housing having one or more openings for a stalk of a plant to pass therethrough, and one or more root chambers for positioning therein of roots of the plant; one or more sealing members coupled to the one or more openings, each sealing member configured to substantially conform to the stalk of the plant and to substantially isolate a canopy of the plant from the one or more root chambers; a nutrient distribution system for introducing nutrients into the one or more root chambers; and a network interface configured to enable the aeroponic system to communicate with an external control system via a computer network.Type: ApplicationFiled: April 13, 2018Publication date: March 21, 2019Inventor: John-Paul Armand Martin
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Patent number: 10116114Abstract: According to the invention, a plurality of elementary laser beams (fi) are generated, the phases of which are adjusted by an electro-optical feedback loop (6, 7i, 8i, 9) implementing the matrix equation of a phase-contrast filtering device (6).Type: GrantFiled: October 14, 2015Date of Patent: October 30, 2018Assignees: COMPAGNIE INDUSTRIELLE DES LASERS CILAS, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE DE LIMOGESInventors: Vincent Kermene, Agnes Desfarges-Berthelemot, Paul Armand, Joel Benoist, David Kabeya, Alain Barthelemy, David Sabourdy, Jean-Eucher Montagne