Patents by Inventor Paul Ashmore
Paul Ashmore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7174476Abstract: Methods and structure for improved tolerance of errors during initialization of a storage volume. More specifically, features and aspects of the invention provide for tolerating read errors during read-modify-write or read-peer-write processing of I/O requests overlapped with initialization of the volume affected by the I/O request. Features and aspects of the system detect such an error and, if the volume is being initialized, attempt graceful recovery of the error rather than shutting down or otherwise disabling the uninitialized volume.Type: GrantFiled: April 28, 2003Date of Patent: February 6, 2007Assignee: LSI Logic CorporationInventors: Paul Ashmore, Theresa Segura
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Publication number: 20060294289Abstract: A method and apparatus for obscuring data held on a storage device associated with a storage system controller are provided. Data is obscured by swapping bit values according to a scrambling key, before the unit of data is stored on the storage device. Furthermore, multiple swaps or translations of bit values can be performed in sequence on a single unit of data. In order to descramble a unit of data, the translations of bit values applied during scrambling are performed in reverse order. Alternatively or in addition, data can be obscured by scrambling the bit values of an address associated with a unit of data.Type: ApplicationFiled: May 17, 2005Publication date: December 28, 2006Applicant: Dot Hill Systems Corp.Inventor: Paul Ashmore
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Publication number: 20060277347Abstract: A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.Type: ApplicationFiled: November 10, 2005Publication date: December 7, 2006Applicant: Dot Hill Systems CorporationInventors: Paul Ashmore, Ian Davies, Gene Maine
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Publication number: 20060248308Abstract: A data storage system configured for efficient operation in a single controller mode and to facilitate an upgrade from single controller operation to dual redundant active-active controller operation is provided. More particularly, a first controller having a segmented write cache is provided. The first segment of the write cache is associated with logical unit numbers (LUNs) owned by the first controller. The second segment is associated with LUNs that are designated as being owned by a second controller. During single controller operation, the segments of the write cache operate as primary write cache. The system may be converted to dual redundant controller operation by adding a second controller having a write cache segmented like the write cache of the first controller. Upon adding a second controller, primary control of the LUNs owned by or zoned to the second controller is taken over by the second controller.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Applicant: Dot Hill Systems Corp.Inventors: Yuanru Wang, Paul Ashmore
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Patent number: 7117320Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.Type: GrantFiled: June 26, 2003Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Paul Ashmore, Matthew John Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
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Publication number: 20060212651Abstract: A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives. Critical data is stored into a first subset of the memory banks, leaving a second subset of memory banks storing only non-critical data. Critical data is data that must be retained during a main power loss to avoid loss of write-cached user data. Critical data includes the write-cached user data itself, as well as metadata describing the write-cached user data. When the controller detects a loss of main power, the controller causes the critical memory banks to receive battery power, but disables battery power to the non-critical memory banks in order to extend the length of time the critical memory banks can continue to receive battery power to reduce the likelihood of user data loss.Type: ApplicationFiled: March 15, 2005Publication date: September 21, 2006Applicant: Dot Hill Systems CorporationInventor: Paul Ashmore
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Publication number: 20060190763Abstract: The present invention is directed to a data storage system utilizing a number of data storage devices. Each of the data storage devices stores primary and mirrored copies of data. Furthermore, the data is arranged such that no one data storage device stores both the primary and mirrored copies of the same chunk of data. Data may be striped across the storage devices such that stripes containing primary copies of data chunks are interleaved with stripes containing mirrored copies of data chunks.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Inventor: Paul Ashmore
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Patent number: 7080208Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).Type: GrantFiled: August 6, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
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Publication number: 20060106982Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.Type: ApplicationFiled: December 22, 2005Publication date: May 18, 2006Applicant: Dot Hill Systems CorporationInventors: Paul Ashmore, Ian Davies, Gene Maine, Rex Vedder
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Publication number: 20060015683Abstract: A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.Type: ApplicationFiled: September 14, 2005Publication date: January 19, 2006Applicant: Dot Hill Systems CorporationInventors: Paul Ashmore, Dwight Lintz, Gene Maine, Victor Pecone, Rex Vedder
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Publication number: 20050283648Abstract: An apparatus for reducing data unavailability time after a loss of main power in a storage controller is described. The controller backs up its volatile memory containing posted-write data to a non-volatile memory upon detecting a loss of main power. The controller continues to provide battery power to the volatile memory to sustain the posted-write data. If the battery is able to supply power to the volatile memory until main power is restored, the controller foregoes restoring the posted-write data to the volatile memory from the non-volatile memory. By not incurring the restore time, which may be substantial if the volatile memory is large since read rates from volatile memories are typically slow, the data unavailability time is reduced. The selective restore feature is user-disableable and also includes a brown-out timer for allowing a user to specify how long to battery-power the volatile memory if the feature is enabled.Type: ApplicationFiled: February 9, 2005Publication date: December 22, 2005Applicant: Dot Hill Systems CorporationInventor: Paul Ashmore
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Publication number: 20050283655Abstract: A RAID controller performing a preemptive reconstruct of a redundant array of disks while the array is still fault-tolerant is disclosed. The controller receives user input specifying an error threshold. When a disk in the array (critical disk) exceeds the error threshold, the controller copies the critical disk data to a spare disk. After the copy completes, the controller replaces the critical disk with the spare disk in the array. The controller keeps the critical disk as part of the redundant array during the copy, i.e., continues to read and write the critical disk in response to user I/O requests. Hence, the array remains fault-tolerant during the preemptive reconstruct. In one embodiment, the controller automatically performs the reconstruct without user intervention. If the critical disk fails during the copy, the controller performs a conventional reconstruct to the spare disk starting where the copy left off.Type: ApplicationFiled: August 4, 2004Publication date: December 22, 2005Applicant: Dot Hill Systems CorporationInventor: Paul Ashmore
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Publication number: 20040216012Abstract: Methods and structure for improved tolerance of errors during initialization of a storage volume. More specifically, features and aspects of the invention provide for tolerating read errors during read-modify-write or read-peer-write processing of I/O requests overlapped with initialization of the volume affected by the I/O request. Features and aspects of the system detect such an error and, if the volume is being initialized, attempt graceful recovery of the error rather than shutting down or otherwise disabling the uninitialized volume.Type: ApplicationFiled: April 28, 2003Publication date: October 28, 2004Inventors: Paul Ashmore, Theresa Segura
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Publication number: 20040049638Abstract: A method for data retention in a data cache and a data storage system are provided. The data storage system (100) includes a storage controller (102) with a cache (103) and a data storage means (106). The cache (103) has a first least recently used list (104) for referencing dirty data which is stored in the cache (103), and a second least recently used list (105) for clean data in the cache (103). Dirty data is destaged from the cache (103) when it reaches the tail of the first least recently used list (104) and clean data is purged from the cache (103) when it reaches the tail of the second least recently used list (105).Type: ApplicationFiled: August 6, 2003Publication date: March 11, 2004Applicant: International Business Machines CorporationInventors: Paul Ashmore, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh
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Publication number: 20040049710Abstract: A method for maintaining data access during failure of a controller in a multiple controller storage subsystem (103) is provided. The storage subsystem (103) has an array of data storage devices (109) and more than one controller (104, 105) for managing the data storage. The method comprises a first controller (201) saving its internal state information (212) and, optionally, resetting itself (213). One or more of the other controllers (202, 203) carry out the steps of pausing operation of the controller (221, 231), saving internal state information of the controller at the time of pausing (222, 232), and continuing operation of the controller (223, 233). The one or more other controllers (202, 203) may pause operation and save their internal state information when they receive a message broadcast (220, 230) from the first controller (201) which has detected an error.Type: ApplicationFiled: June 26, 2003Publication date: March 11, 2004Applicant: International Business Machines CorporationInventors: Paul Ashmore, John Matthew Fairhurst, Michael Huw Francis, Robert Bruce Nicholson, Simon Walsh, Barry John Wood
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Publication number: 20030200394Abstract: An arrangement and methods for operation in a cache memory system to facitate re-synchronising non-volatile cache memories (150B, 160B) following interruption in communication. A primary adapter (150) creates a non-volatile record (150C) of each cache update before it is applied to either cache. Each such record is cleared when the primary adapter knows that the cache update has been applied to both adapters' caches. In the event of a reset or other failure, the primary adapter can read the non-volatile list of transfers which were ongoing. For each entry in this list, the primary adapter negotiates with the secondary adapter (160) and transfers only the data which may be different.Type: ApplicationFiled: April 3, 2003Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: Paul Ashmore, Michael Huw Francis, Simon Walsh