Patents by Inventor Paul B. Rawlins
Paul B. Rawlins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9195462Abstract: A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.Type: GrantFiled: April 11, 2007Date of Patent: November 24, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zheng Xu, Suraj Bhaskaran, Jason T. Nearing, Paul B. Rawlins
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Patent number: 8122437Abstract: In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.Type: GrantFiled: March 31, 2008Date of Patent: February 21, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Zheng Xu, Suraj Bhaskaran, Klas M. Bruce, Jason T. Nearing, Paul B. Rawlins, Matt B. Smittle, Michael D. Snyder
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Publication number: 20090249302Abstract: In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Zheng Xu, Suraj Bhaskaran, Klas M. Bruce, Jason T. Nearing, Paul B. Rawlins, Matt B. Smittle, Michael D. Snyder
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Publication number: 20080256339Abstract: A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Zheng Xu, Suraj Bhaskaran, Jason T. Nearing, Paul B. Rawlins
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Patent number: 6961800Abstract: Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.Type: GrantFiled: September 28, 2001Date of Patent: November 1, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Patent number: 6829665Abstract: A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.Type: GrantFiled: September 28, 2001Date of Patent: December 7, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Phillip M. Jones, Paul B. Rawlins, Kenneth T. Chin
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Patent number: 6823409Abstract: A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.Type: GrantFiled: September 28, 2001Date of Patent: November 23, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Phillip M. Jones, Paul B. Rawlins
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Publication number: 20030070016Abstract: A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.Type: ApplicationFiled: September 28, 2001Publication date: April 10, 2003Inventors: Phillip M. Jones, Paul B. Rawlins
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Publication number: 20030065843Abstract: A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Phillip M. Jones, Paul B. Rawlins, Kenneth T. Chin
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Publication number: 20030065860Abstract: An internal bus structure for a multi-processor-bus system. More specifically, an internal bus protocol/structure is described. The internal bus structure includes unidirectional, point-to-point connections between control modules. The individual buses carry unique transactions corresponding to a request. Each transaction includes an identification tag. The present protocol provides for efficient communication between processors, peripheral devices, memory and coherency modules. The present protocol and design scheme is generic in that the techniques are scalable and re-usable.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Publication number: 20030065844Abstract: Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Patent number: 6510522Abstract: A computer system, bus interface unit, and method are provided for securing certain devices connected to an I2C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I2C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I2C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I2C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I2C bus or addressed device thereon.Type: GrantFiled: November 20, 1998Date of Patent: January 21, 2003Assignee: Compaq Information Technologies Group, L.P.Inventors: David F. Heinrich, Hung Q. Le, Paul B. Rawlins, Charles J. Stancil
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Patent number: 6480097Abstract: A personal computer provides security features enabling control over access to data retained in the computer. The computer is secured by having the system ROM provide a password at power-on to a security device which controls access to the secured features. Once a password has been downloaded to the security device, a Protect Resources command is issued to the security device. To gain access to the secured feature after boot-up, the user provides the correct password to the security device and waits for approval from the security device. Since the security device only verifies the password and does not divulge it, security of the system is enhanced. Once access to protected resources is no longer required, the computer issues another Protect Resources command to the security device to once more lock access to the protected resources.Type: GrantFiled: January 20, 1999Date of Patent: November 12, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Timothy R. Zinsky, Charles N. Shaver, Roger A. Kaiser, Jr., Paul B. Rawlins
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Patent number: 6363439Abstract: A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.Type: GrantFiled: December 7, 1998Date of Patent: March 26, 2002Assignee: Compaq Computer CorporationInventors: John D. Battles, Paul B. Rawlins, Robert Allan Lester, Patrick L. Ferguson
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Patent number: 6263395Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.Type: GrantFiled: January 6, 1999Date of Patent: July 17, 2001Assignee: Compaq Computer Corp.Inventors: Patrick L. Ferguson, Paul B. Rawlins, David F. Heinrich, Robert L. Woods
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Patent number: 6216183Abstract: A computer system, bus interface unit and method are provided for securing passwords entered upon a USB input device, such as a USB keyboard. The bus interface unit includes a USB host controller coupled between a USB bus on which the keyboard is configured and another bus on which the system memory is operably connected. The host controller contains registers which keep track of target endpoint addresses of USB devices and, more specifically, address locations (i.e., an input/output address range of to-be-secured data) within those devices. Entry upon a keyboard which falls within the monitored, target endpoint address noted within the host controller will signal the host controller to initiate system management interrupt (SMI), and to execute SMI handler code attributed to SMI. Data from the secured (monitored) target address space is placed within a data buffer of the host controller and eventually to a secured location within system memory.Type: GrantFiled: November 20, 1998Date of Patent: April 10, 2001Assignee: Compaq Computer CorporationInventor: Paul B. Rawlins
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Patent number: 5963142Abstract: A personal computer provides security features enabling control over access to data retained in the computer. The computer is secured by having the system ROM provide a password at power-on to a security device which controls access to the secured features. Once a password has been downloaded to the security device, a Protect Resources command is issued to the security device. To gain access to the secured feature after boot-up, the user provides the correct password to the security device and waits for approval from the security device. Since the security device only verifies the password and does not divulge it, security of the system is enhanced. Once access to protected resources is no longer required, the computer issues another Protect Resources command to the security device to once more lock access to the protected resources.Type: GrantFiled: January 6, 1997Date of Patent: October 5, 1999Assignee: Compaq Computer CorporationInventors: Timothy R. Zinsky, Charles N. Shaver, Roger A. Kaiser, Jr., Paul B. Rawlins