Abstract: A Fault-tolerant computer architecture employs a plurality of microcomputers connected in a partially meshed ring. Three device controllers are connected to any of the microcomputers by means of a passive switch, and a fault in data transmission relative to one microcomputer is resolved by a two-out-of-three decision. A failure of one microcomputer is manifested by an adjacent microcomputer, so that the down microcomputer is omitted from furthwr task assignments.

Abstract: In a data transmitting/receiving device having parallel/serial and serial/parallel character conversion, particularly for data exchange between communicating data processing systems, and being arranged between a local data processing system and a data modem terminating a data communication line for the purpose of controlling data transmission and/or reception procedures and containing a procedure store, and in which a random access storage is provided as a data buffer for intercepting data jams is provided along with an interrupt control for interrupting processing operations in a microprocessor in respect of higher processing priority, and in which a timer is provided for setting optimum transmission speed, first and second modem connection lines are provided and data messages to be transmitted are converted bit-oriented or character-oriented by the microprocessor from data groups supplied thereto by means of corresponding input switching commands.

Abstract: A data transmission/reception installation with parallel/serial and serial/parallel character conversion is disclosed which relieves the respective local data processing installation of all tasks connected with data transmission procedures. Both a temporal vitiation of the data processing operations as well as a reduction of the memory capacity available for the data processing operations are avoided. The data transmission/reception installation disclosed has a data transmission processor arranged within the respective data processing system between the local data processing installation and a data modem terminating a data line for controlling data transmission and reception procedures. The data transmission processor contains at least one microprocessor and a transcribable program memory. A cyclic redundancy check generator is provided by means of which a data transmission and reception monitoring corresponding to a stored test program can be carried out.