Patents by Inventor Paul Blinzer
Paul Blinzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220413732Abstract: Methods and apparatuses for transferring data from non-volatile memory to process accelerator memory are disclosed. In one embodiment, a process accelerator issues a transfer request for a resource at a host file system. The process accelerator receives, responsive to the transfer request, data from the host file system, wherein the data corresponds to the resource and the process accelerator receives the data directly from the host file system bypassing staging memory of the host. The process accelerator manipulates the data to obtain the resource. Thus, the process accelerator may obtain the resource directly from the host file system to minimize the number of transfers of the data.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Inventor: PAUL BLINZER
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Patent number: 11494211Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.Type: GrantFiled: April 22, 2019Date of Patent: November 8, 2022Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20220269621Abstract: An electronic device includes a processor that executes one or more guest operating systems and an input-output memory management unit (IOMMU). The IOMMU accesses, for/on behalf of each guest operating system among the one or more guest operating systems, IOMMU memory-mapped input-output (MMIO) registers in a separate copy of a set of IOMMU MMIO registers for that guest operating system.Type: ApplicationFiled: January 11, 2021Publication date: August 25, 2022Inventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20220179784Abstract: A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Applicant: Advanced Micro Devices, Inc.Inventor: Paul Blinzer
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Patent number: 11042495Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.Type: GrantFiled: September 20, 2019Date of Patent: June 22, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Maggie Chan, Philip Ng, Paul Blinzer
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Patent number: 11003588Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.Type: GrantFiled: August 22, 2019Date of Patent: May 11, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Sonu Arora, Paul Blinzer, Philip Ng, Nippon Harshadk Raval
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Publication number: 20210089480Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.Type: ApplicationFiled: September 20, 2019Publication date: March 25, 2021Inventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20210056042Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Sonu ARORA, Paul BLINZER, Philip NG, Nippon Harshadk RAVAL
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Patent number: 10909053Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.Type: GrantFiled: May 27, 2019Date of Patent: February 2, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20200387326Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20200379927Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.Type: ApplicationFiled: May 27, 2019Publication date: December 3, 2020Inventors: Maggie Chan, Philip Ng, Paul Blinzer
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Publication number: 20200334058Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.Type: ApplicationFiled: April 22, 2019Publication date: October 22, 2020Inventors: Maggie Chan, Philip Ng, Paul Blinzer
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Patent number: 10761736Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.Type: GrantFiled: August 6, 2018Date of Patent: September 1, 2020Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Nima Osqueizadeh, Paul Blinzer
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Patent number: 10467138Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.Type: GrantFiled: December 28, 2015Date of Patent: November 5, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Ali Ibrahim, Benjamin T. Sander, Vydhyanathan Kalyanasundharam
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Publication number: 20180349057Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Applicants: ATI Technologies ULC, ADVANCED MICRO DEVICES, INC.Inventors: Nima OSQUEIZADEH, Paul BLINZER
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Publication number: 20180181341Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicant: Advanced Micro Devices, Inc.Inventor: Paul Blinzer
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Patent number: 10007464Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.Type: GrantFiled: December 23, 2016Date of Patent: June 26, 2018Assignee: Advanced Micro Devices, Inc.Inventor: Paul Blinzer
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Publication number: 20170185514Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.Type: ApplicationFiled: December 28, 2015Publication date: June 29, 2017Inventors: Paul Blinzer, Ali Ibrahim, Benjamin T. Sander, Vydhyanathan Kalyanasundharam
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Patent number: 9423847Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.Type: GrantFiled: December 20, 2011Date of Patent: August 23, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Krishna S Bernucho, Maurice B Steinman, Ming L. So, Mom-Eng Ng, Xiaogang Zheng, Paul Blinzer, Francisco L Duran, Walter G. Fry, Ali Ibrahim, Andrew W. Lueck, Dan P Shimizu, Gary H. Simpson, Laura M. Smith
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Patent number: 9239804Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.Type: GrantFiled: October 3, 2013Date of Patent: January 19, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Andrew Kegel, Jimshed Mirza, Paul Blinzer, Philip Ng