Abstract: Systems, devices, and methods for relieving muscle pain that may include a massage roller; one or more arms at least partially disposed within the massage roller, wherein each arm of the one or more arms has a length greater than the diameter of the massage roller and slides freely across the diameter of the massage roller; and two or more movable protuberances, where each of the two or more movable protuberances is disposed at each end of each arm.

Abstract: Technologies for managing data object requests in a storage node cluster include a proxy computing node communicatively coupled to the cluster of storage nodes. The proxy computing node is configured to receive data object requests from a communicatively coupled client computing device and identify a plurality of storage nodes of the cluster at which the data object of the data object request is stored. The proxy computing node is further configured to determine which of the identified storage nodes from which to retrieve the stored data object and transmit a request for the data object. Additionally, the proxy computing node is configured to estimate a request completion time based on a service time and a wait time for each of the identified storage nodes, as well as identify which of the storage nodes to retrieve the stored data object from based on the estimated request completion times. Other embodiments are described and claimed.

Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.

Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract: Technologies for managing data object requests in a storage node cluster include a proxy computing node communicatively coupled to the cluster of storage nodes. The proxy computing node is configured to receive data object requests from a communicatively coupled client computing device and identify a plurality of storage nodes of the cluster at which the data object of the data object request is stored. The proxy computing node is further configured to determine which of the identified storage nodes from which to retrieve the stored data object and transmit a request for the data object. Additionally, the proxy computing node is configured to estimate a request completion time based on a service time and a wait time for each of the identified storage nodes, as well as identify which of the storage nodes to retrieve the stored data object from based on the estimated request completion times. Other embodiments are described and claimed.

Abstract: A method for determining a threshold crack length in a machine component including a fatigue crack defining a fatigue crack length and a fatigue crack angle. The method includes determining a component threshold stress intensity factor for the fatigue crack angle, determined from a dataset that includes threshold stress intensity factors for mixed-mode phase angles formed by conducting an asymmetric four point bend test on a test specimen having an initial notch. The method includes determining a threshold crack length based on the component fatigue crack length and fatigue crack angle using a formula disclosed herein.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract: A heterogeneous processor architecture is described.

Abstract: In some embodiments, a client computer includes a memory, a client presence program adapted to be located in the memory, and a processor. The processor is coupled to the memory and is adapted to execute the client presence program to receive provider presence information from an instant messaging (IM) server and to store the provider presence information in the memory. The provider presence information includes at least a provider status for at least one service provider.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract: A heterogeneous processor architecture is described.