Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, for instance qubits, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Superconductor technology and Batcher banyan switching technology are combined and implemented as a practical component in a single cryo-MCM substrate (10) containing a plurality of superconductor chips (37, 38, 39, 41, 42, 43, 44, 46, 48, 49, 51, 53 and 55) arranged in a plurality of rows and columns. Wiring (52) on the substrate connects the chips in each row of a number of the columns (41, 43, 45, 47, 49, 51 & 53) serially to collectively define a Batcher sorter. Other wiring (52) connects the chips in each row of a number of other columns (40, 42, 44 & 48) in reverse banyan and banyan networks. The foregoing includes a novel superconductor Batcher two-bit serial sorter (FIG. 8) and trap (FIG. k9).

Abstract: Superconductor technology and Batcher banyan switching technology are combined and implemented as a practical component in a single cryo-MCM substrate (10) containing a plurality of superconductor chips (37, 38, 39, 41, 42, 43, 44, 46, 48, 49, 51, 53 and 55) arranged in a plurality of rows and columns. Wiring (52) on the substrate connects the chips in each row of a number of the columns (41, 43, 45, 47, 49, 51 & 53) serially to collectively define a Batcher sorter. Other wiring (52) connects the chips in each row of a number of other columns (40, 42, 44 & 48) in reverse banyan and banyan networks. The foregoing includes a novel superconductor Batcher two-bit serial sorter (FIG. 8) and trap (FIG. k9).