Abstract: The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.

Abstract: Methods and apparatus for conditioning communications signals based on detection of high-frequency in the polar domain. High-frequency events detected in a phase-difference component of a complex baseband signal in the polar domain are detected and used as a basis for performing hole-blowing on the complex baseband signal in the quadrature domain and/or nonlinear filtering either or both the magnitude and phase-difference components in the polar domain. Alternatively, high-frequency events detected in the phase-difference signal that correlate in time with low-magnitude events detected in a magnitude component of the complex baseband signal are used as a basis for performing hole-blowing on the complex baseband signal in the quadrature domain and/or nonlinear filtering either or both the magnitude and phase-difference components in the polar domain.

Abstract: Methods and apparatus for reducing high-frequency events in polar domain signals. An exemplary method includes first generating an unmodified rectangular-coordinate signal having in-phase (I) and quadrature phase (Q) components that are modulated according to a predetermined modulation scheme. Next a first sample of the unmodified rectangular-coordinate signal is modified based on how close the first sample is to the origin in the complex signal plane and how fast a signal trajectory between the first sample and a subsequent sample changes. Finally, the modified rectangular-coordinate signal is converted to a polar domain signal having amplitude and phase components. By modifying the first sample in this manner, either or both the amplitude and phase components have reduced high-frequency content compared to a polar domain signal that would be generated without the first sample having been first modified.

Abstract: A radio frequency (RF) transmitter has at least one digital signal processing module and at least one power amplifier module. The digital signal processing module includes at least one digital pre-distortion component arranged to receive at least one complex input signal, perform two-dimensional non-uniform mapping of the complex input signal to a first, in-phase, digital pre-distortion control word and a further, quadrature, digital pre-distortion control word, and output the in-phase and quadrature pre-distortion digital control words. The power amplifier module includes a first, in-phase, array of switch-mode power cells and at least one further, quadrature, array of switch-mode power cells. The two-dimensional non-uniform mapping has a pre-distortion profile at least partly based on an input/output relationship for the power amplifier module arranged to generate an analogue RF signal based at least partly on the in-phase and quadrature digital pre-distortion control words.

Abstract: A radio frequency (RF) transmitter including at least one digital signal processing module is described. The at least one digital signal processing module is arranged to receive a complex digital input signal, successively apply pre-distortion to the received complex digital input signal with a progressively finer granularity, simultaneously progressively increase a sampling rate of the received complex digital input signal, and output a first, in-phase digital control word and a second, quadrature, digital control word for controlling at least one digital power amplifier component to generate an RF signal representative of the received complex digital input signal.

Abstract: A radio frequency (RF) transmitter architecture includes at least one digital signal processing module. The at least one digital signal processing module is configurable to operate in at least a first mode wherein the at least one digital signal processing module is arranged to receive a digital input signal, select, from a reduced set of digital power amplifier (DPA) control values, a plurality of DPA control values based at least partly on the received digital input signal, perform interpolation of the plurality of selected DPA control values to determine a DPA control value from a non-reduced set of DPA control values representative of the received digital input signal, and output to at least one DPA component the determined DPA control value representative of the received digital input signal.

Abstract: Methods and apparatuses for reducing noise in frequency to digital converters (FDCs). An FDC apparatus includes a first FDC, a second FDC and a combiner. The first and second FDCs are configured to independently sample an input signal according to a sample clock to generate first and second digital signals, each representing the instantaneous frequency of the input signal. The combiner is configured to form a resultant digital signal from the first and second digital signals. The first and second FDCs are designed and combined in the noise-canceling FDC apparatus so that the first and second signals they generate have correlated noise profiles in a frequency range of interest. When combined by the combiner to form the resultant digital signal, the resultant digital signal has a signal power to noise power ratio greater than the signal power to noise power ratios characterizing the first and second digital signals of the individual first and second FDCs.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: A transmitter generates first and second constant-envelope radio frequency (RF) component signals having first and second phase angles. The first and second phases are controlled by a phase controller. First and second nonlinear power amplifiers (PAs) are modulated by an amplitude-modulated power supply signal as the first and second constant-envelope RF component signals are amplified. The phase controller controls the first and second phases of the first and second constant-envelope RF component signals, in response to a power control signal, and, in so doing, controls an effective load impedance seen at the outputs of the first and second nonlinear PAs. By controlling the effective load impedance in response to a power control signal, rather than in response to rapid amplitude variations in an input signal envelope, the output power of the transmitter is efficiently controlled over a wide dynamic range even at low output powers.

Abstract: A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: Methods and apparatus for transmitting communications signals that are both power efficient and effective at avoiding or reducing transmitter-generated receive band noise. An exemplary transceiver apparatus includes a multi-mode transmitter that is configurable to operate in a plurality of operating modes (e.g., a polar mode, a quadrature mode and a hybrid mode), a receiver, and an operating mode controller. The operating mode controller is configured to control which operating mode the transmitter is to operate, depending on one or more of a transmit (Tx) power, receive (Rx) power, the Tx power relative to the Rx power, a level of frequency separation between a Tx frequency band and a Rx frequency band (Tx/Rx band separation), and modulation type employed by the transmitter.

Abstract: A multiple-mode modulator is configured similarly to a direct conversion quadrature modulator with an infusion of an amplitude modulation signal path from a large signal polar modulator to improve the power amplifier efficiency. The multiple-mode modulator also includes a radio frequency signal path. The multiple-mode modulator is configured to receive a baseband signal, convert the baseband signal to a radio frequency (RF) signal, and to process the RF signal according to either a polar mode or a quadrature mode, depending on a time-varying input voltage of the RF signal. When the power amplifier operates in the linear region, the RF signal is processed according to the quadrature mode. When the power amplifier operates in the compressed region, the RF signal is processed according to the polar mode. The multiple-mode modulator can be configured according to a small signal polar architecture or a large signal polar architecture, having either an open-loop or closed-loop configuration.

Abstract: A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

Abstract: Envelope tracking (ET) methods and systems for controlling the delivery of power to radio frequency power amplifiers (RFPAs). An exemplary ET system includes an RFPA and a wide bandwidth capable and power efficient envelope modulator that includes a first power supplying apparatus and a second power supplying apparatus. The first power supplying apparatus includes a switch-mode converter and a regulator. The first mode converter is operable to dynamically step down a fixed power supply voltage according to amplitude variations in an envelope signal received by the regulator, and use the resulting dynamic power supply signal to power the regulator. The second power supplying apparatus is connected in parallel with the first power supplying apparatus. Depending on a power of an output signal to be generated at an output of the power amplifier, power is supplied to the power amplifier from either or both of the first and second power supplying apparatuses.

Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.

Abstract: A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

Abstract: The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.