Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.

Abstract: LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces.

Abstract: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Abstract: A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces. For those LGA types made by molding techniques such as the metal-in-polymer type (eg. Tyco Electronics MPI, or Shin Etsu RP) or the Metal-on-Elastomer type (IBM), using molds with the desired topography provides the desired LGA topography.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

Abstract: A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.

Abstract: Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.

Abstract: A probe structure for an electronic device is provided. In one aspect, the probe structure includes an electrically insulating carrier having one or more contact structures traversing a plane thereof. Each contact structure includes an elastomeric material having an electrically conductive layer running along at least one surface thereof continuously through the plane of the carrier. The probe structure includes one or more other contact structures adapted for connection to a test apparatus.

Abstract: In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2 m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.

Abstract: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Abstract: A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.

Abstract: A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.

Abstract: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.