Abstract: Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.

Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Abstract: According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.

Abstract: Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.

Abstract: According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.

Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Abstract: A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.

Abstract: Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.

Abstract: A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: A system and method to regulate voltage on a chip are described. The system includes a central controller to output a digital code based on a voltage measurement from a sense point on a power grid of the chip. The system also includes a plurality of micro-regulators, each of the plurality of micro-regulators outputting a respective voltage to the power grid based on the digital code.

Abstract: A system and method to regulate voltage on a chip are described. The system includes a central controller to output a digital code based on a voltage measurement from a sense point on a power grid of the chip. The system also includes a plurality of micro-regulators, each of the plurality of micro-regulators outputting a respective voltage to the power grid based on the digital code.

Abstract: A voltage regulator includes a regulator input connected to a reference voltage; a regulator output that outputs a regulated voltage to an electrical load; a first loop, the first loop configured to receive the reference voltage, the first loop outputting a bias voltage; a second loop, the second loop configured to receive the bias voltage as an input; and a bias voltage capacitor connected to a node between the first loop and the second loop.

Abstract: Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.

Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.

Abstract: Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.