Abstract: Transistors in a transistor array constructed in a testable multiple channel decoder are tested by setting the array in a test mode. A stuck low test, which detects an open circuit between a source and drain of a transistor, is executed by providing all address lines a first predetermined logic value. A stuck high test, which detects a short between a source and drain of a transistor, is executed by providing a first address line tested a second predetermined logic value and a second logic address line tested the first logic value.

Abstract: A method and apparatus for post-packaging testing of one-time programmable memories provided means for assuring that each cell of the memory will appear to a customer to be erased and that it is capable of being programmed. The preferred embodiment of the invention is a microcomputer including one-time programmable memory, but the invention also includes memory-only devices. Marginal reading method and apparatus provide for detecting the threshold voltage of memory cells below the level at which the cell appears to the customer to be erased and marginal programming method and apparatus provide for slightly increasing the threshold voltage of cells in order to ensure their programmability.

Abstract: A method and apparatus for post-packaging testing of one-time programmable memories provides means for assuring that each cell of the memory will appear to a customer to be erased and that it is capable of being programmed. The preferred embodiment of the invention is a microcomputer including one-time programmable memory, but the invention also includes memory-only devices. Marginal reading method and apparatus provide for detecting the threshold voltage of memory cells below the level at which the cell appears to the customer to be erased and marginal programming method and apparatus provide for slightly increasing the threshold voltage of cells in order to ensure their programmability.

Abstract: A single-chip microcomputer comprises at least two separate and independent electrically erasable programmable read only memories (EEPROMs) on-board which may be independently programmed, erased and read. Each part of the split EEPROM has its own data bus and address bus. Programming and erasing is controlled by a program register which has separate bits for configuring and latching the data and address buses of a selected EEPROM array, for providing programming voltage to the array of choice and for choosing between programming and erasing the selected array. The split EEPROM provides versatility to the user in allowing one part of the EEPROM to be programmed while the program stored in another part of the EEPROM or RAM may be read and utilized. In addition, test time and effort of the microcomputer may be considerably reduced.

Abstract: A semaphore register for use in a peripheral controller includes a semaphore bit which when not set indicates the availability of a shared resource, an internal ownership bit which when set indicates ownership of the resource by a peripheral controller and an external ownership bit which when set indicates ownership of the resource by a host processor. If the semaphore is clear, upon receipt of a read signal from the peripheral controller, the semaphore bit and the internal ownership bit are set. Upon receipt of a read signal from the host processor, the semaphore bit and the external ownership bit are set. Arbitration logic includes means responsive to simultaneous reads by the host processor and the peripheral controller for indicating to the host processor that the resource is unavailable thus giving priority to the peripheral controller. The semaphore bit may be reset by write signals from either the peripheral controller or the host processor.

Abstract: A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.