Patents by Inventor Paul E. Nicollian

Paul E. Nicollian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and circuit for simulating gate-to-drain breakdown
    Patent number: 8554531
    Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Paul E. Nicollian, Riza T. Cakici
  • SYSTEM AND CIRCUIT FOR SIMULATING GATE-TO-DRAIN BREAKDOWN
    Publication number: 20120043619
    Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul E. NICOLLIAN, Riza T. CAKICI
  • Semiconductor device having a dielectric layer with a uniform nitrogen profile
    Publication number: 20030157773
    Abstract: A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.
    Type: Application
    Filed: March 13, 2003
    Publication date: August 21, 2003
    Inventors: Jerry Hu, Paul E. Nicollian, Kwame N. Eason, Rajesh Khamankar, Mark S. Rodder, Sunil Hattangady
  • Semiconductor device having a dielectric layer with a uniform nitrogen profile
    Publication number: 20030080389
    Abstract: A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Inventors: Jerry Hu, Kwame N. Eason, Rajesh Khamankar, Mark S. Rodder, Paul E. Nicollian, Sunil Hattangady