Abstract: The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second address transition signals to enable data storage in a single memory address. A comparator is coupled to the first and second ports (1) for detecting address transitions indicating that the second port is addressing a particular memory address coincidentally when the first port also is addressing the same memory address, and (2) for generating a busy output signal for that address in the event of such coincidence. A transition detection circuit is used to detect the transition resulting from the removal of the busy output signal from the comparator and for providing a busy removal output signal equivalent to an address detection signal in the event of such detection.

Abstract: The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adapted to be connected to one terminal of a power supply and a second node adapted to be connected to the other node, and having an input for receiving an input signal and an output for providing an output signal adapted to be connected to an output transistor. The circuit also has a first MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series with the first node of the inverter circuit, and a second MOS transistor opposite in either polarity type or mode from the first MOS transistor, having its source-drain circuit coupled in series with the other node of the inverter circuit.