Abstract: An interface for receiving and transmitting serial data from and to a communications bus and for permitting access to the data by a processor, after the data has been converted to parallel form. The interface makes use of two random access memories. A read memory stores incoming data from the communications bus and is read by the processor. A write memory, to which the processor may write, stores outgoing data to place on the communications bus. These memories are controlled by programmable logic devices, programmed so that the processor is interrupted at a selected time interval for service to the memories. Special features include a dual access mode, in which the processor may operate on incoming data in place.