Patents by Inventor Paul Edward HANHAM
Paul Edward HANHAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11847037Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.Type: GrantFiled: September 16, 2020Date of Patent: December 19, 2023Assignee: KIOXIA CORPORATIONInventors: Paul Edward Hanham, Shigehiro Asano, Julien Margetts
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Patent number: 11394402Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).Type: GrantFiled: January 4, 2021Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio
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Publication number: 20220083442Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.Type: ApplicationFiled: September 16, 2020Publication date: March 17, 2022Applicant: Toshiba Memory CorporationInventors: Paul Edward HANHAM, Shigehiro ASANO, Julien MARGETTS
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Publication number: 20210126653Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).Type: ApplicationFiled: January 4, 2021Publication date: April 29, 2021Inventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio
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Patent number: 10886947Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).Type: GrantFiled: December 20, 2018Date of Patent: January 5, 2021Assignee: Toshiba Memory CorporationInventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio
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Patent number: 10747613Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.Type: GrantFiled: September 7, 2018Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio, Senthilkumar Diraviam, Jonghyeon Kim
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Publication number: 20200201708Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio
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Patent number: 10613927Abstract: A method for fast calculation of a frame error rate (FER) of an error correcting code (ECC) soft decoder using a soft read process includes determining an MI-FER conversion data structure based on a relationship between mutual information (MI) of input channels and output channels of a memory, and FER of the ECC soft decoder, and decoding an encoded data codeword stored in a memory page of the memory and read using a soft read process. The method further includes generating a set of joint probability values using the information from the soft read process and data indicating true bit values for the data codeword, determining an MI value using the set of joint probability values, and determining an FER estimate using the MI-FER conversion data structure.Type: GrantFiled: March 9, 2018Date of Patent: April 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: David Malcolm Symons, Paul Edward Hanham, Francesco Giorgio
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Publication number: 20200081773Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.Type: ApplicationFiled: September 7, 2018Publication date: March 12, 2020Inventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio, Senthilkumar Diraviam, Jonghyeon Kim
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Patent number: 10404279Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.Type: GrantFiled: September 21, 2018Date of Patent: September 3, 2019Assignee: Toshiba Memory CorporationInventors: Paul Edward Hanham, David Malcolm Symons, Neil Buxton
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Publication number: 20190103882Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.Type: ApplicationFiled: September 21, 2018Publication date: April 4, 2019Inventors: Paul Edward Hanham, David Malcolm Symons, Neil Buxton
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Patent number: 10084479Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.Type: GrantFiled: July 7, 2014Date of Patent: September 25, 2018Assignee: Toshiba Memory CorporationInventors: Paul Edward Hanham, David Malcolm Symons, Neil Buxton
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Patent number: 9407294Abstract: A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.Type: GrantFiled: July 7, 2014Date of Patent: August 2, 2016Assignee: Kabushi Kaisha Toshiba.Inventors: Paul Edward Hanham, David Malcolm Symons, Neil Buxton
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Publication number: 20160006459Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.Type: ApplicationFiled: July 7, 2014Publication date: January 7, 2016Inventors: Paul Edward HANHAM, David Malcolm SYMONS, Neil BUXTON
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Publication number: 20160006462Abstract: A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.Type: ApplicationFiled: July 7, 2014Publication date: January 7, 2016Inventors: Paul Edward HANHAM, David Malcolm SYMONS, Neil BUXTON