Patents by Inventor Paul F. Barnes

Paul F. Barnes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7709861
    Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Agere Systems Inc.
    Inventors: Parag Madhani, Paul F. Barnes, Donald E. Hawk, Jr., Kandaswamy Prabakaran
  • Publication number: 20080061319
    Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.
    Type: Application
    Filed: March 12, 2007
    Publication date: March 13, 2008
    Applicant: Agere Systems Inc.
    Inventors: Parag Madhani, Paul F. Barnes, Donald E. Hawk, Kandaswamy Prabakaran
  • Patent number: 7271485
    Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die with at least two IO buffers. One of the IO buffers is located a distance from a particular package pin and another of the IO buffers is located a greater distance from the particular package pin. The IO buffer located closest to the package pin includes first bond pad electrically coupled to a circuit implementing a first interface type and a first floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type and a second floating bond pad.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: September 18, 2007
    Assignee: Agere Systems Inc.
    Inventors: Parag N. Madhani, Paul F. Barnes, Donald E. Hawk, Jr., Kandaswamy Prabakaran
  • Patent number: 5977897
    Abstract: An integrated circuit includes a string of substantially similarly-shaped resistive cells, each cell having a first resistive portion and a second resistive portion, the string having an overall orientation and at least one cell, preferably substantially all cells, and more preferably all cells have their respective centerlines oriented at non-orthogonal angles, preferably about 45 degrees, relative to the overall orientation. The cells are contiguous such that a resistor is formed by the first resistive portion of one cell and the second resistive portion of an adjacent cell. The cells preferably have a substantially hexagonal shape and are arranged into substrings. If the string includes a folding point, substrings immediately adjacent to the folding point should include an odd number, preferably three, of cells, and substrings not adjacent to the folding point should comprise an even number, preferably two, of cells.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: November 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Paul F. Barnes, Ramin Khoini-Poorfard