Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: An applicator instrument for dispensing surgical fasteners includes a housing, a firing system disposed in the housing and being moveable in distal and proximal directions along a first axis, and an elongated shaft extending from the housing, the elongated shaft having a proximal section and a distal section that is oriented at an angle relative to the proximal section. A plurality of surgical fasteners are disposed in the elongated shaft. The applicator instrument has a handle that extends upwardly from the housing along a second axis that defines an acute angle with the first axis. A trigger is mounted on the handle, and a linkage couples the trigger with the handle and the firing system. When the trigger is squeezed, the linkage guides the trigger along a linear path of movement relative to the handle.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: An applicator instrument for dispensing surgical fasteners includes a housing defining a bottom of the applicator instrument, a firing system disposed in the housing and being moveable in distal and proximal directions along a first axis, a handle extending upwardly from the housing along a second axis that defines an acute angle with the first axis, the handle having an upper end that defines a top of the applicator instrument, and a trigger mounted on the handle for actuating the firing system. The applicator instrument includes an elongated shaft extending from the housing, the elongated shaft having a proximal section that extends along the first axis and a distal section that is oriented at an angle relative to the proximal section for extending upwardly toward the top of the application instrument. A distal end cap has a proximally sloping distal face and a dispensing window for dispensing surgical fasteners.

Abstract: A method and system for detecting and controller wafer surface pressure distribution. Detecting and controlling wafer surface pressure distribution comprises measuring in situ wafer uniformity of a wafer at a plurality of locations of the wafer; and in response to the measured wafer uniformity controlling through a feedback loop in situ CMP head pressure applied at the plurality of locations of the wafer in real time to polish the wafer.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Abstract: A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Abstract: A phacoemulsification cannula 10 includes a hub 18 for engagement with a surgical instrument 30. An elongated needle 12 has a proximal end 14 attached to the hub 18 and a distal end 16. The needle 12 has first and second inner diameters 22 and 24. The first inner diameter 22 is larger than the second inner diameter 24, and a transition 26 from the first inner diameter 22 to the second inner diameter 24 is closer to the proximal end 14 than to the distal end 16.

Abstract: A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Abstract: The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract: The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.