Abstract: Systems and methods for an electroactive polymer actuated dot structure is disclosed herein. According to an aspect, an actuated dot structure includes a housing. The actuated dot structure also includes a pin configured to move between a first position and a second position with respect to the housing. Further, the actuated dot structure includes a multimorph engaged with the pin and configured to displace the pin between the first and second positions and to latch the pin in the second position.

Abstract: Systems and methods for an electroactive polymer actuated dot structure is disclosed herein. According to an aspect, an actuated dot structure includes a housing. The actuated dot structure also includes a pin configured to move between a first position and a second position with respect to the housing. Further, the actuated dot structure includes a multimorph engaged with the pin and configured to displace the pin between the first and second positions and to latch the pin in the second position.

Abstract: A method for selectively assembling a molecular device on a substrate comprises contacting the first substrate with a solution containing molecular devices; impeding bonding of the molecular devices to the substrate such that application of a voltage potential to the substrate results in assembly of the molecular device on the substrate at a rate that is at least 1.5 times the rate of assembly of the molecular device on a voltage-neutral substrate; and applying a voltage potential to the substrate so as to cause the molecular devices to assemble on the substrate. A nanoscale computing device is described that includes a substrate, a pair of conductive input/output electrodes carried on this substrate and disposed in spaced-apart relationship and a substantially disordered assembly of nanowires formed on the substrate in a region between the electrodes, thereby forming at least one programmable conductive pathway between the pair of electrodes.

Abstract: An assembly of a NanoCell comprising a disordered array of metallic islands interlinked with molecules between metallic input/output leads and with disordered arrays of molecules and Au islands is disclosed. The NanoCell may function both as a memory device that is programmable post-fabrication. The assembled NanoCells exhibit reproducible switching behavior and at least two types of memory effects at room temperature. The switch-type memory is characteristic of a destructive read while the conductivity-type memory features a nondestructive read. Both types of s memory effects are stable for more than a week at room temperature and bit level ratios (0:1) of the conductivity-type memory have been observed to be as high as 104:1 and reaching 106:1 upon ozone treatment which likely destroys extraneous leakage pathways.

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.