Patents by Inventor Paul G. Chan
Paul G. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103301Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have displays that produce images. Positioners may be used to move the displays relative to the eye positions of a user's eyes. An adjustable optical system may include tunable lenses such as tunable cylindrical liquid crystal lenses. The displays may be viewed through the lenses when the user's eyes are at the eye positions. A sensor may be incorporated into the head-mounted display to measure refractive errors in the user's eyes. The sensor may include waveguides and volume holograms, and a camera for gathering light that has reflected from the retinas of the user's eyes. Viewing comfort may be enhanced by adjusting display positions relative to the eye positions and/or by adjusting lens settings based on the content being presented on the display and/or measured refractive errors.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Inventors: Victoria C. Chan, Christina G. Gambacorta, Graham B. Myhre, Hyungryul Choi, Nan Zhu, Phil M. Hobson, William W. Sprague, Edward A. Valko, Qiong Huang, Branko Petljanski, Paul V. Johnson, Brandon E. Clarke, Elijah H. Kleeman
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Patent number: 10552334Abstract: A method and system acquires cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method and system, a store queue is accessed for one or more portions of a cache line associated with the load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.Type: GrantFiled: March 24, 2017Date of Patent: February 4, 2020Assignee: INTEL CORPORATIONInventors: Karthikeyan Avudaiyappan, Paul G. Chan
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Publication number: 20170199822Abstract: A method and system acquires cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method and system, a store queue is accessed for one or more portions of a cache line associated with the load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.Type: ApplicationFiled: March 24, 2017Publication date: July 13, 2017Inventors: Karthikeyan AVUDAIYAPPAN, Paul G. CHAN
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Patent number: 9632947Abstract: A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.Type: GrantFiled: August 19, 2013Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Karthikeyan Avudaiyappan, Paul G. Chan
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Publication number: 20150052303Abstract: A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Paul G. Chan
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Patent number: 8370576Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. At least some of the active memory operations access the memory in an execution order that is different from the program order. The circuit includes a first memory that caches data accessed by the memory operations. This memory is partitioned into N banks. Checkpoint entries, which are stored in a second memory also partitioned into N banks, are associated with each trace. Each entry refers to a checkpoint location in the first memory. A sub-circuit receives rollback requests and responds by overwriting checkpoint locations. Each of the N memory units consisting of a bank in the first memory and the corresponding bank in the second memory may be rolled back independently and concurrently with other memory units.Type: GrantFiled: February 13, 2008Date of Patent: February 5, 2013Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 8370609Abstract: This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Violations of the ordering constraints result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.Type: GrantFiled: February 13, 2008Date of Patent: February 5, 2013Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 8051247Abstract: A circuit for tracking memory operations with trace-based execution is disclosed. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Executing one of the active memory operations updates a checkpoint location. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. After the trace is committed, all of the checkpoint entries associated with the trace are invalidated.Type: GrantFiled: February 13, 2008Date of Patent: November 1, 2011Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 8024522Abstract: A processor includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. The circuit also includes a sub-circuit that holds memory operation ordering information corresponding to the active memory operations. The sub-circuit detects violations of ordering constraints.Type: GrantFiled: February 13, 2008Date of Patent: September 20, 2011Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 8019944Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Violations of the ordering constraints may be signaled too late to prevent an update of the cached data associated with the memory operations. A sub-circuit detects this condition and invalidates the checkpoint locations indicated by the checkpoint entries associated with the trace experiencing the violation and all younger traces.Type: GrantFiled: February 13, 2008Date of Patent: September 13, 2011Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 8010745Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.Type: GrantFiled: February 13, 2008Date of Patent: August 30, 2011Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 7877630Abstract: This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.Type: GrantFiled: February 13, 2008Date of Patent: January 25, 2011Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 7779307Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.Type: GrantFiled: February 13, 2008Date of Patent: August 17, 2010Assignee: Oracle America, Inc.Inventors: John Gregory Favor, Paul G. Chan, Graham Ricketson Murphy, Joseph Byron Rowlands
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Patent number: 7644221Abstract: A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions.Type: GrantFiled: April 11, 2005Date of Patent: January 5, 2010Assignee: Sun Microsystems, Inc.Inventors: Paul G. Chan, Ricky C. Hetherington