Abstract: A circuit for coupling the demodulated composite video signal to a Video Tape Recorder and for selectively coupling either that signal or a signal from an alternate source to the receivers video processing circuitry. The circuit includes diodes having inputs separately connected to the set of video signal sources and outputs coupled in common to a control circuit that determines which signal is coupled to the output and which is isolated from it.

Abstract: In a VIR-responsive Tint Control system a dematrixing circuit for synthesizing, from the individual chrominance demodulator outputs, a ZERO-COLOR reference signal. The VIR chrominance interval signal and the ZERO-COLOR reference signals are used as input to a feedback loop that also includes the receiver's chrominance subcarrier oscillator. By comparing the VIR chrominance interval signal to the synthesized ZERO-COLOR reference subcarrier oscillator phase errors are corrected by virtue of a single sampling of the VIR signal.

Abstract: A video processing system for a television receiver is shown. The video processing system includes a gain controlled stage through which a video signal is coupled. The gain of the stage is controlled to provide contrast control of the video signal. The video signal is also applied to an aperture correction circuit which develops an aperture correction signal including a pre-shoot transient responses. The aperture correction signal is also coupled through the gain controlled stage so that it is amplified or attenuated by the same amount as the video signal. An automatic peaking control circuit receives the pre-shoot and over-shoot signals to generate an automatic control signal to control the gain of the aperture correction circuit. A tracking control circuit causes the automatic peaking control circuit to accurately track the setting of an adjustable control which controls the gain of the aperture correction circuit.

Abstract: A vertical synchronizing circuit wherein a counter counts pulses at twice the horizontal deflection rate and provides a vertical output pulse at a predetermined count is shown. A synchronism or mode detector causes the circuit to switch to a driven mode when the counter is not reset in synchronism with the vertical synchronizing pulses. The mode detector causes the circuit to switch to a countdown mode when synchronism is detected. A phase detector detects phase errors between the counter and the vertical synchronizing pulses when the circuit is in the countdown mode and causes the counter to delete or add counts depending upon the direction of the phase error when such phase errors persist for a predetermined number of vertical fields. The vertical synchronizing pulses are applied to a gate which is enabled in the countdown mode when the counter reaches a predetermined count shortly before a vertical synchronizing pulse is anticipated.