Abstract: A time of day (TOD) synchronizer in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: A time of day (TOD) synchronization mechanism in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: A time of day (TOD) synchronizer in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.

Abstract: A time of day (TOD) synchronization mechanism in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.

Abstract: A method, data processing system, and computer program product for verifying the functionality of a digital circuit. The method includes transmitting sequences of parallel data packets via parallel data transfer paths. Prior to receipt of at least two of the transmitted sequences, a first skew is introduced between the at least two of the transmitted sequences. This introduction includes inserting one or more parallel control data packets in the transmitted sequences, and erasing one of the control data packets, replacing one of the control data packets, and inserting another control data packet in one of the sequences. The method includes determining if an expected indicator signal is provided in the form of an overflow indicator or an underflow indicator.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.