Abstract: A processor and auxiliary processor for use in a digital data processing system, the auxiliary processor processing selected instructions, such as floating point instructions. The processor and auxiliary processor are interconnected by status lines, data lines and a bus to which other units in the system may also be connected. When the processor begins processing a selected instruction, it passes the instruction's operation code to the auxiliary processor over the data lines and enables the operands to be transferred to the auxiliary processor over the bus, along with information concerning each operand, which is transferred over the data lines. The processor then signals over the status lines that it is ready to receive the results. The auxiliary processor, when it has finished executing the special instruction, transmits a code over the status lines indicating it is sending the results, and transmits the condition codes over the data lines and the result data over the bus.

Abstract: The invention provides a system for controlling the storage of information in a cache memory and features a processor to be connected to a bus, the bus including information signal transfer lines for transferring information signals and a cache control signal transfer line for transferring a cache control signal having a plurality of conditions, the processor including a cache memory and a bus interface circuit connected to the cache memory and for connection to the bus, the bus interface circuit including: i. an information signal transfer circuit for performing a read operation in which it receives information signals from the information signal transfer lines, the information signal transfer circuit transferring the received information signals to the cache memory; and ii.

Abstract: A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurances, such as a context switch, which cannot be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.

Abstract: A processor for use in a digital data processing system including a main memory and one or more input/output units. The processor includes a cache memory. When the processor retrieves data, it may, in response to the condition of internal flags conditioned by the operating system, be stored in the cache. Even if the flags enable retrieved data to be cached, the main memory or input/output units may assert a signal which disables caching.

Abstract: A processor for use in a digital data processing system includes a bus interface circuit for transferring data to and from other units in the system and for controlling the transfer of information within the processor over an internal bus. The bus interface circuit includes two state machines, one for controlling the internal transfers of information, and the other for controlling the external transfers of information. The state machines communicate through flags which indicate when external operations are pending. A plurality of latches are provided to receive write data, a write address and a read address from other portions of the processor, and an input latch receives signals from other units in the system, thereby allowing both a wire operation and a read operation to be initiated at the same time. The processor continues operating unless another operation is required.