Abstract: A transmit processor that includes a transmit frequency domain equalizer (TX FEQ) that pre-compensates packets in the frequency domain to flatten transmit filter response to improve the spectral mask and reduce packet error rate (PER). The TX FEQ taps may be selected so that the average power at the output equalize the average power applied to the input. The TX FEQ may be designed to yield 64 QAM packets with no quantization distortion at the input of the an Inverse Fast Fourier Transform (IFFT) processor. The 64 QAM constellation map points and TX FEQ gain values are selected to avoid exceeding the bit resolution of the IFFT processor. The tones may be bound together into zones to reduce implementation complexity by reducing the number of TX FEQ taps.

Abstract: A wireless receiver including a receive chain, a synchronization processor, a memory, a combiner and a soft decision processor. The synchronization processor determines a frequency response of the wireless channel using synchronization data transmitted in the wireless channel. The memory stores a compensation vector indicative of a frequency response of receive chain filtering. The combiner combines the compensation vector with the wireless channel frequency response to provide a compensated frequency response. The soft decision processor uses the compensated frequency response to evaluate data decisions. The compensation vector is based on measurement or estimation of the frequency response of the receive chain. The combiner may be based on multiplication or addition. The wireless receiver may include an FEQ. The synchronization processor generates FEQ coefficients for programming the FEQ taps.

Abstract: An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate.

Abstract: An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate.

Abstract: A wireless receiver including a receive chain, a synchronization processor, a memory, a combiner and a soft decision processor. The synchronization processor determines a frequency response of the wireless channel using synchronization data transmitted in the wireless channel. The memory stores a compensation vector indicative of a frequency response of receive chain filtering. The combiner combines the compensation vector with the wireless channel frequency response to provide a compensated frequency response. The soft decision processor uses the compensated frequency response to evaluate data decisions. The compensation vector is based on measurement or estimation of the frequency response of the receive chain. The combiner may be based on multiplication or addition. The wireless receiver may include an FEQ. The synchronization processor generates FEQ coefficients for programming the FEQ taps.

Abstract: A method and system for determining gain taps values for a pre-compensation transmit frequency domain equalizer of a wireless transmitter. Each tap of the equalizer scales a zone and each zone includes at least one sub-carrier. To reduce the number of taps, one or more zones may incorporate more than one sub-carrier. The method includes providing test information for processing by the transmitter, measuring sub-carrier magnitudes generated by the transmitter, normalizing the measured sub-carrier magnitudes, determining an average power value of the normalized sub-carrier magnitudes within each sub-carrier zone, and finding a gain value for each sub-carrier zone so that when multiplied by the average power value of that sub-carrier zone comes closest to a predetermined target value. The normalizing, determining and finding may be repeated for multiple target values to generate a multiple arrays of gain values, where one array that is closest to achieving a unity power gain is selected.

Abstract: A transmit processor that includes a transmit frequency domain equalizer (TX FEQ) that pre-compensates packets in the frequency domain to flatten transmit filter response to improve spectral mask and reduce PER. The TX FEQ taps may be selected so that the average power at output equals the average power applied to the input. The TX FEQ may be designed to yield 64 QAM packets with no quantization distortion at the input of an Inverse Fast Fourier Transform (IFFT) processor. The 64 QAM constellation map points and TX FEQ gain values are selected to avoid exceeding the bit resolution of the IFFT processor. The tones may be bound together into zones to reduce implementation complexity by reducing the number of TX FEQ taps.