Abstract: In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an interface to the register file to switch register windows in the register file in response to one or more window swap operations. The sources of window swap operations and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the interface. In one particular implementation, for example, block signals may be used from higher priority sources to lower priority sources to block issuance of window swap operations by the lower priority sources.

Abstract: A method and system of processing a cryptographic packet includes receiving a first cryptographic packet in a host CPU. A first set of data required to execute the first cryptographic packet is identified. The first cryptographic packet and the required first set of data is transferred to a cryptographic co-processor. The first cryptographic packet is executed in the cryptographic co-processor. The host CPU is notified that the execution of the first cryptographic packet is complete. The executed first cryptographic packet is received in the host CPU.

Abstract: In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

Abstract: An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.

Abstract: A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely. Both program-related exceptions and hardware errors are detected and, without being corrected by the hardware, flow down the pipeline to a trap unit where they are prioritized and handled via software. The processor assigns each instruction a thread ID and error information as it follows the pipeline. The trap unit records the error by using the thread ID of the instruction and the pipelined error information in order to determine which ESR receives the information and what to store in the ESR. A trap handling routine is then initiated to facilitate error recovery.

Abstract: An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag parity value in a RAM portion of a TLB, using the CAM key input to generate a tag parity check value for a matched entry, and comparing the generated tag parity check value to the stored tag parity value to determine if there is a parity match or error.

Abstract: A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.

Abstract: In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages. The first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages. The first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and a first instruction entering the second pipeline stage is from the first thread.

Abstract: A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

Abstract: A processor core for transitioning a debugging unit between a plurality of operating states generates trace data as it processes operating signals of an instruction stream. The processor core provides a trigger event signal to the debugging unit in response to a trigger instruction signal within the instruction stream that is representative of triggering instruction for transitions debugging unit to one of (1) a base operating state, (2) a dynamic storage operating state or (3) a static storage operating state. Concurrently or alternatively, the processor core can provide the trigger event signal to the debugging unit as a function of generated trigger data in response to additional operational instructions within the instruction stream.

Abstract: A method and system of processing a cryptographic packet includes receiving a first cryptographic packet in a host CPU. A first set of data required to execute the first cryptographic packet is identified. The first cryptographic packet and the required first set of data is transferred to a cryptographic co-processor. The first cryptographic packet is executed in the cryptographic co-processor. The host CPU is notified that the execution of the first cryptographic packet is complete. The executed first cryptographic packet is received in the host CPU.

Abstract: Aspects for soft error detection for a superscalar microprocessor are described. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.

Abstract: A processor core for transitioning a debugging unit between a plurality of operating states in response to an instruction stream is disclosed. The processor core generates trace data as it processes operating signals of the instruction stream. The processor core provides a first trigger event signal to the debugging unit in response to a first trigger instruction signal within the instruction stream that is representative of a triggering instruction to transitions the debugging unit to a base operating state. The processor core provides a second trigger event signal to the debugging unit in response to a second trigger instruction signal within the instruction stream that is representative of a triggering instruction to dynamically store trace data within the memory component of the debugging unit.