Abstract: A gas processing system for recovering methane gas from a landfill includes a high pressure main absorber plus a relatively low pressure one. The low pressure absorber receives a gas stream from an equally low pressure flash tank. This low pressure gas stream consists mostly of carbon dioxide and methane. The methane would normally be lost due to the high cost of recompressing the carbon dioxide, but by running this mixture of carbon dioxide and methane through the low pressure absorber with a slip stream of cold absorbent, a large portion of the carbon dioxide can be removed with negligible methane losses. The remaining methane can be recycled through the high pressure main absorber without having to recompress the removed portion of carbon dioxide.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.

Abstract: A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.

Abstract: A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.

Abstract: In representative embodiments, a memory architecture is provided that includes a main bus, at least one CPU, a cache memory that caches the CPU, and a coherency control that determines the existence or location of a data request received from the main bus in the processor or the cache.

Abstract: A computer system has multiple agents sharing a resource. When a request for access to the shared resource is denied, a counter is initialized. Each subsequent transaction for the shared resource is counted. When the counter reaches a threshold, the priority of the access request is increased. The threshold may be programmable. Requests may be sorted into queues, with each queue having a separately programmable threshold. Multiple requests from one queue may then be granted without interruption. In an example embodiment, a cache memory has multiple queues, and each queue has an associated counter with a programmable threshold.

Abstract: A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.

Abstract: The invention describes a system for and a method of using multiple queues to access memory entities. Priorities can be established between competing queues to allow maximum processing efficiency. Additionally, when more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions.

Abstract: A method and apparatus automatically determines a phase-based relationship between two clocks generated from the same source. In accordance with the present invention, a clock generator provides a clock signal to a sending IC and a receiving IC. The sending IC transmits data to the receiving IC over a data bus, and provides a strobe signal that is delayed by ¼ of a cycle of the internal clock of the sending IC to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four round robin clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC.

Abstract: An electrical interface connects a conductive pins to a printed circuit board. The electrical interface includes an elastomer holder having a plurality of holes. Elastomer conductors are placed in the plurality of holes within the elastomer holder. The elastomer holder is then attached to the printed circuit board so that each elastomer conductor comes into contact with a conductive pad on the printed circuit board. The conductive pins are placed in electrical contact with the elastomer conductors, for example, through a conductive socket. In the preferred embodiment the elastomer holder is composed of printed circuit board material. Before the elastomer holder is connected to the printed circuit board, the elastomer conductors are held in the holes in the elastomer holder using a throw-away retainer.