Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.

Abstract: Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell.

Abstract: A memory is modified so that read and write data are transferred on both rising and falling edges of a timing signal, thereby essentially doubling the data transfer rate from memory. In one embodiment, a dual-edge extended data out (DE.sup.2 DO) memory includes modified and improved circuits and operating methods, as compared to a standard extended data out (EDO) memory, so that read and write data are transferred on both rising and falling edges of a timing signal. In a described embodiment, DE.sup.2 DO dynamic RAM (DRAM) reads and writes data on the rising and falling edges of a column address strobe (CAS) timing signal. By transferring data on both the rising and falling edges of the timing signal, the data transfer rate to and from the memory is effectively doubled.

Abstract: Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.

Abstract: A system and method for a dynamic random access memory. The dynamic random access memory further comprises a memory block and a plurality of data lines. The memory block further comprises a plurality of memory cells. The plurality of memory cells are arranged into a plurality of rows and a plurality of columns. The plurality of data lines is proportional to the plurality of columns. Each of the plurality of data lines is substantially parallel to the plurality of columns.