Patents by Inventor Paul M. Fuller
Paul M. Fuller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6889357Abstract: Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.Type: GrantFiled: May 10, 2000Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Brian Johnson, Terry R. Lee, Paul M. Fuller
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Patent number: 6550026Abstract: A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.Type: GrantFiled: November 27, 2000Date of Patent: April 15, 2003Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Hua Zheng, Paul M. Fuller
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Patent number: 6154860Abstract: A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.Type: GrantFiled: May 27, 1999Date of Patent: November 28, 2000Assignee: Micron Technology, IncInventors: Jeffrey P. Wright, Hua Zheng, Paul M. Fuller
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Patent number: 6055611Abstract: A method and apparatus for selectively enabling and disabling access to prime and redundant memory elements based on an address to a prime memory element is described. By receiving a prime element address and comparing it to program defective addresses, a signal indicating a correspondence between addresses is provided when a match occurs. The indication may be used as a select signal to a multiplexer for selecting between inputs. Moreover, an indication of a correspondence between addresses may be latched for temporary storage. The signal indicating whether or not a match has been found is provided to an override circuit, which selectively determines which enable signals are to be active and which are to be inactive. This allows for access to a prime element, a redundant element instead of a prime element, a redundant element instead of a prime and/or a redundant element, and so on. Additionally, a timing control enable signal may be employed to control timing of providing an enable signal.Type: GrantFiled: July 9, 1997Date of Patent: April 25, 2000Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Paul M. Fuller
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Patent number: 5966388Abstract: A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.Type: GrantFiled: January 6, 1997Date of Patent: October 12, 1999Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Hua Zheng, Paul M. Fuller
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Patent number: 5945845Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.Type: GrantFiled: July 9, 1998Date of Patent: August 31, 1999Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Paul M. Fuller
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Patent number: 5783948Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.Type: GrantFiled: October 7, 1996Date of Patent: July 21, 1998Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Paul M. Fuller