Patents by Inventor Paul M. Petersen
Paul M. Petersen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10540254Abstract: Technologies for analyzing persistent memory programs include a computing device having persistent memory. The computing device executes a persistent memory program that includes one or more store operations to the persistent memory. The computing device records persistent memory store events of the persistent memory program and constructs a load dependency graph of the persistent memory program. The persistent memory store events may include persistent memory stores, cache flush events, memory fence events, and persistent memory commit events. The computing device replays the persistent memory store events and analyzes the load dependency graph. The computing device may identify persistency programming errors in the persistent memory program. The computing device may identify persistent memory commit points of the persistent memory program. The computing device may identify groups of persistent memory store operations to persist atomically. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2016Date of Patent: January 21, 2020Assignee: Intel CorporationInventors: Zhiqiang Ma, Paul M. Petersen
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Patent number: 10089696Abstract: Embodiments of techniques and systems for slowdown-budget-aware event information collection are described. In various embodiments, a system may be configured to control collection of information for events associated with execution of a program during execution of the program based on a slowdown cost budget. In various embodiments, the slowdown cost budget may be set in order to help keep slowdown experienced due to associated event information collection within a range around the budget. In embodiments, this may provide a user with greater control over the effects of the associated event information collection and instrumentation than would be available due to simple sampling rate control. Other embodiments may be described and claimed.Type: GrantFiled: May 9, 2012Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Zhiqiang Ma, Paul M. Petersen
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Patent number: 9690552Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.Type: GrantFiled: December 27, 2014Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Hongbo Rong, Peng Tu, Tatiana Shpeisman, Hai Liu, Todd A. Anderson, Youfeng Wu, Paul M. Petersen, Victor W. Lee, P. G. Lowney, Arch D. Robison, Cheng Wang
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Publication number: 20170132094Abstract: Technologies for analyzing persistent memory programs include a computing device having persistent memory. The computing device executes a persistent memory program that includes one or more store operations to the persistent memory. The computing device records persistent memory store events of the persistent memory program and constructs a load dependency graph of the persistent memory program. The persistent memory store events may include persistent memory stores, cache flush events, memory fence events, and persistent memory commit events. The computing device replays the persistent memory store events and analyzes the load dependency graph. The computing device may identify persistency programming errors in the persistent memory program. The computing device may identify persistent memory commit points of the persistent memory program. The computing device may identify groups of persistent memory store operations to persist atomically. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2016Publication date: May 11, 2017Inventors: Zhiqiang Ma, Paul M. Petersen
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Patent number: 9594899Abstract: A power charger includes a first storage area to store control software, a charging circuit to send power through an interface, and a processor to generate at least one control signal based on the control software. The power to be sent through the interface is to charge a battery of a device coupled to the interface, and the at least one control signal includes information to cause a monitoring operation to be performed to determine a status of the device.Type: GrantFiled: December 30, 2011Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Bevin R. Brett, Paul M. Petersen
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Patent number: 9489246Abstract: A method and device for determining parallelism of tasks of a program comprises generating a task data structure to track the tasks and assigning a node of the task data structure to each executing task. Each node includes a task identification number and a wait number. The task identification number uniquely identifies the corresponding task from other currently executing tasks and the wait number corresponds to the task identification number of a node corresponding to the last descendant task of the corresponding task that was executed prior to a wait command. The parallelism of the tasks is determined by comparing the relationship between the tasks.Type: GrantFiled: September 30, 2011Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Jeffrey V. Olivier, Zhiqiang Ma, Paul M Petersen
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Publication number: 20160188305Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventors: Hongbo Rong, Peng Tu, Tatiana Shpeisman, Hai Liu, Todd A. Anderson, Youfeng Wu, Arthur N. Glew, Paul M. PetersEn, Victor W. Lee, P.G. Lowney, Arch D. Robinson, Cheng Wang
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Patent number: 8887174Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.Type: GrantFiled: July 26, 2011Date of Patent: November 11, 2014Assignee: Intel CorporationInventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
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Publication number: 20140207632Abstract: Embodiments of techniques and systems for slowdown-budget-aware event information collection are described. In various embodiments, a system may be configured to control collection of information for events associated with execution of a program during execution of the program based on a slowdown cost budget. In various embodiments, the slowdown cost budget may be set in order to help keep slowdown experienced due to associated event information collection within a range around the budget. In embodiments, this may provide a user with greater control over the effects of the associated event information collection and instrumentation than would be available due to simple sampling rate control. Other embodiments may be described and claimed.Type: ApplicationFiled: May 9, 2012Publication date: July 24, 2014Inventors: Zhiqiang Ma, Paul M. Petersen
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Patent number: 8732142Abstract: A method of removing a first data race condition by generating a list of suggested solutions is provided. The method comprises detecting the first data race condition involving a shared resource that is accessed first by a first thread and then by a second thread; suggesting one or more solutions using a lockset mechanism; suggesting one or more solutions using a vector clock mechanism; suggesting that a user create a new synchronization object; suggesting that a user replicate the shared resource; and displaying the list to the user.Type: GrantFiled: March 31, 2008Date of Patent: May 20, 2014Assignee: Intel CorporationInventors: Paul M Petersen, Zhiqiang Ma
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Publication number: 20140013428Abstract: A power charger includes a first storage area to store control software, a charging circuit to send power through an interface, and a processor to generate at least one control signal based on the control software. The power to be sent through the interface is to charge a battery of a device coupled to the interface, and the at least one control signal includes information to cause a monitoring operation to be performed to determine a status of the device.Type: ApplicationFiled: December 30, 2011Publication date: January 9, 2014Inventors: Bevin R. Brett, Paul M. Petersen
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Publication number: 20130290975Abstract: A method and device for determining parallelism of tasks of a program comprises generating a task data structure to track the tasks and assigning a node of the task data structure to each executing task. Each node includes a task identification number and a wait number. The task identification number uniquely identifies the corresponding task from other currently executing tasks and the wait number corresponds to the task identification number of a node corresponding to the last descendant task of the corresponding task that was executed prior to a wait command. The parallelism of the tasks is determined by comparing the relationship between the tasks.Type: ApplicationFiled: September 30, 2011Publication date: October 31, 2013Inventors: Jeffrey V. Olivier, Zhiqiang Ma, Paul M. Petersen
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Patent number: 8205200Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.Type: GrantFiled: November 29, 2005Date of Patent: June 19, 2012Assignee: Intel CorporationInventors: Shih-wei Liao, Ryan N. Rakvic, Richard A. Hankins, Hong Wang, Gansha Wu, Guei-Yuan Lueh, Xinmin Tian, Paul M. Petersen, Sanjiv Shah, Trung Diep, John Shen, Gautham Chinya
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Patent number: 8141082Abstract: A method for detecting race conditions in a concurrent processing environment is provided. The method comprises implementing a data structure configured for storing data related to at least one task executed in a concurrent processing computing environment, each task represented by a node in the data structure; and assigning to a node in the data structure at least one of a task number, a wait number, and a wait list; wherein the task number uniquely identifies the respective task, wherein the wait number is calculated based on a segment number of the respective task's parent node, and wherein the wait list comprises at least an ancestor's wait number. The method may further comprise monitoring a plurality of memory locations to determine if a first task accesses a first memory location, wherein said first memory location was previously accessed by a second task.Type: GrantFiled: February 28, 2008Date of Patent: March 20, 2012Assignee: Intel CorporationInventors: Gautam Upadhyaya, Zhiqiang Ma, Paul M. Petersen
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Publication number: 20120017221Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.Type: ApplicationFiled: July 26, 2011Publication date: January 19, 2012Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
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Patent number: 8010969Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.Type: GrantFiled: June 13, 2005Date of Patent: August 30, 2011Assignee: Intel CorporationInventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, Shivnandan D. Kaushik, Bryant E. Bigbee, John P. Shen, Trung A. Diep, Xiang Zou, Baiju V. Patel, Paul M. Petersen, Sanjiv M. Shah, Ryan N. Rakvic, Prashant Sethi
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Publication number: 20090248689Abstract: A method of removing a first data race condition by generating a list of suggested solutions is provided. The method comprises detecting the first data race condition involving a shared resource that is accessed first by a first thread and then by a second thread; suggesting one or more solutions using a lockset mechanism; suggesting one or more solutions using a vector clock mechanism; suggesting that a user create a new synchronization object; suggesting that a user replicate the shared resource; and displaying the list to the user.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Paul M. Petersen, Zhiqiang Ma
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Publication number: 20090222825Abstract: A method for detecting race conditions in a concurrent processing environment is provided. The method comprises implementing a data structure configured for storing data related to at least one task executed in a concurrent processing computing environment, each task represented by a node in the data structure; and assigning to a node in the data structure at least one of a task number, a wait number, and a wait list; wherein the task number uniquely identifies the respective task, wherein the wait number is calculated based on a segment number of the respective task's parent node, and wherein the wait list comprises at least an ancestor's wait number. The method may further comprise monitoring a plurality of memory locations to determine if a first task accesses a first memory location, wherein said first memory location was previously accessed by a second task.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Inventors: Gautam Upadhyaya, Zhiqiang Ma, Paul M. Petersen
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Publication number: 20090125519Abstract: A method, apparatus and system for, in a computing apparatus, comparing a measure of data contention for a group of operations protected by a lock to a predetermined threshold for data contention, and comparing a measure of lock contention for the group of operations to a predetermined threshold for lock contention, eliding the lock for concurrently executing two or more of the operations of the group using two or more threads when the measure of data contention is approximately less than or equal to the predetermined threshold for data contention and the measure of lock contention is approximately greater than or equal to a predetermined threshold for lock contention, and acquiring the lock for executing two or more of the of operations of the group in a serialized manner when the measure of data contention is approximately greater than or equal to the predetermined threshold for data contention and the measure of lock contention is approximately less than or equal to a predetermined threshold for lock conteType: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Inventors: Arch D. Robison, Paul M. Petersen
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Patent number: 7500242Abstract: The present disclosure relates to acquiring and releasing a shared resource via a lock semaphore and, more particularly, to acquiring and releasing a shared resource via a lock semaphore utilizing a state machine.Type: GrantFiled: September 8, 2003Date of Patent: March 3, 2009Assignee: Intel CorporationInventors: Sanjiv M. Shah, Paul M. Petersen, Grant E. Haab