Abstract: A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.

Abstract: A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.

Abstract: A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.

Abstract: A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.

Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.

Abstract: A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.

Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.

Abstract: A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.