Patents by Inventor Paul McHardy

Paul McHardy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for automatic hierarchical design partitioning
    Patent number: 10339243
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 2, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Scott James Brissenden, Paul McHardy
  • METHOD AND APPARATUS FOR AUTOMATIC HIERARCHICAL DESIGN PARTITIONING
    Publication number: 20180189427
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 5, 2018
    Inventors: Scott James Brissenden, Paul McHardy
  • Method and apparatus for automatic hierarchical design partitioning
    Patent number: 9922156
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 20, 2018
    Assignee: Altera Corporation
    Inventors: Scott James Brissenden, Paul McHardy
  • Method and apparatus for automatic hierarchical design partitioning
    Patent number: 8832618
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Altera Corporation
    Inventors: Scott James Brissenden, Paul McHardy
  • Method and apparatus for automatic hierarchical design partitioning
    Patent number: 8255847
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: August 28, 2012
    Assignee: Altera Corporation
    Inventors: Scott James Brissenden, Paul McHardy
  • Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
    Patent number: 7594204
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: September 22, 2009
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Paul McHardy, Chris Sanford, Gabriel Quan, Terry Borer, Ian Chesal, Valavan Manohararajah, Ivan Hamer, Stephen D. Brown
  • Method and apparatus for performing logic replication in field programmable gate arrays
    Patent number: 7257800
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: August 14, 2007
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Gabriel Quan, Terry Borer, Valavan Manohararajah, Paul McHardy, Ivan Hamer, Karl Schabas, Kevin Chan