Patents by Inventor Paul R. de la Houssaye
Paul R. de la Houssaye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11615318Abstract: A pattern recognition device comprising: a coupled network of damped, nonlinear, dynamic elements configured to generate an output response in response to at least one environmental condition, wherein each element has an associated multi-stable potential energy function that defines multiple energy states of an individual element, and wherein the elements are tuned such that environmental noise triggers stochastic resonance between energy levels of at least two elements; a processor configured to monitor the output response over time and to determine a probability that the pattern recognition device is in a given state based on the monitored output response; and detecting a pattern in the at least one environmental condition based on the probability.Type: GrantFiled: July 23, 2021Date of Patent: March 28, 2023Assignee: United States of America as represented by the Secretary of the NavyInventors: Paul R. De La Houssaye, Benjamin J. Migliori, Adi Ratan Bulsara, Chriswell Hutchens, Justin M. Mauger
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Publication number: 20220051053Abstract: A pattern recognition device comprising: a coupled network of damped, nonlinear, dynamic elements configured to generate an output response in response to at least one environmental condition, wherein each element has an associated multi-stable potential energy function that defines multiple energy states of an individual element, and wherein the elements are tuned such that environmental noise triggers stochastic resonance between energy levels of at least two elements; a processor configured to monitor the output response over time and to determine a probability that the pattern recognition device is in a given state based on the monitored output response; and detecting a pattern in the at least one environmental condition based on the probability.Type: ApplicationFiled: July 23, 2021Publication date: February 17, 2022Inventors: Paul R. De La Houssaye, Benjamin J. Migliori, Adi Ratan Bulsara, Chriswell Hutchens, Justin M. Mauger
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Publication number: 20210256305Abstract: A pattern recognition device comprising: a coupled network of damped, nonlinear, dynamic elements configured to generate an output response in response to at least one environmental condition, wherein each element has an associated multi-stable potential energy function that defines multiple energy states of an individual element, and wherein the elements are tuned such that environmental noise triggers stochastic resonance between energy levels of at least two elements; a processor configured to monitor the output response over time and to determine a probability that the pattern recognition device is in a given state based on the monitored output response; and detecting a pattern in the at least one environmental condition based on the probability.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Inventors: Paul R. De La Houssaye, Benjamin J. Migliori, Adi Ratan Bulsara, Chriswell Hutchens, Justin M. Mauger
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Patent number: 11093794Abstract: A pattern recognition device comprising: a coupled network of damped, nonlinear, dynamic elements configured to generate an output response in response to at least one environmental condition, wherein each element has an associated multi-stable potential energy function that defines multiple energy states of an individual element, and wherein the elements are tuned such that environmental noise triggers stochastic resonance between energy levels of at least two elements; a processor configured to monitor the output response over time and to determine a probability that the pattern recognition device is in a given state based on the monitored output response; and detecting a pattern in the at least one environmental condition based on the probability.Type: GrantFiled: February 13, 2020Date of Patent: August 17, 2021Assignee: United States of America as represented by the Secretary of the NavyInventors: Paul R. De La Houssaye, Benjamin J. Migliori, Adi Ratan Bulsara, Chriswell Hutchens, Justin M. Mauger
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Patent number: 8309371Abstract: A system and method include forming an optical cavity by positioning a photonic crystal a predetermined distance from a substrate, and creating, within the cavity, a standing wave having a substantially flat wavefront. The standing wave may be created by applying an input wave to a first surface of the photonic crystal. The predetermined distance may be such that a peak intensity of the standing wave is proximate to or a calculated distance from the substrate surface. The peak intensity may vary in relation to the substrate surface. The method may include tuning the peak intensity location within the cavity by shifting the wavelength of the input wave or altering the characteristics of the photonic crystal by an external field. A second photonic crystal may be used on the other side of the substrate to replace the reflecting properties of the substrate, allowing for further smoothing of the wavefront.Type: GrantFiled: July 21, 2009Date of Patent: November 13, 2012Assignee: The United States of America as represented by the Secretary of the NavyInventors: Paul R. De La Houssaye, J. Scott Rodgers
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Patent number: 8211730Abstract: A method for manufacture of a nanophotonic device can include the step of operatively coupling a planar light source and a photodetector with an optical waveguide. The planar light source, photodetector and optical waveguide can then be monolithically integrated in direct contact with a sapphire substrate, along with an electronic component that is also in direct contact with the sapphire substrate.Type: GrantFiled: September 29, 2011Date of Patent: July 3, 2012Assignee: The United States of America as represented by the Secretary of the NavyInventors: Serey Thai, Paul R. de la Houssaye, Randy L. Shimabukuro, Stephen D. Russell
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Patent number: 8063473Abstract: A nanophotonic device. The device includes a substrate, at least one light emitting structure and at least one electronic component. The at least one light emitting structure is capable of transmitting light and is monolithically integrated on the substrate. The at least one electronic component is monolithically integrated on the substrate. A method for fabricating nanophotonic devices is also described.Type: GrantFiled: November 29, 2004Date of Patent: November 22, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Serey Thai, Paul R. de la Houssaye, Randy L. Shimabukuro, Stephen D. Russell
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Patent number: 8057388Abstract: A microsensor array system, comprising a pad, a plurality of actuators attached to the pad, and a plurality of microprobes, wherein substantially each microprobe in the plurality of microprobes is attached to a respective actuator in the plurality of actuators.Type: GrantFiled: April 10, 2008Date of Patent: November 15, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Paul R. de la Houssaye, Jamie K. Pugh, William Pugh, Dennis E. Amundson, Howard W. Walker
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Patent number: 7388247Abstract: A high precision microelectromechanical capacitor with programmable voltage source includes a monolithic MEMS device having a capacitance actuator, a trim capacitor, and a high precision, programmable voltage source. The trim capacitor has a variable capacitance value, preferably for making fine adjustments in capacitance. The capacitance actuator is preferably mechanically coupled to and electrically isolated from the trim capacitor and is used to control the capacitance value of the trim capacitor. The capacitance adjustment of the trim capacitor is non-destructive and may be repeated indefinitely. The trim capacitor may be adjusted by mechanically changing the distance between its electrodes. The programmable voltage source provides a highly accurate and stable output voltage potential corresponding to control signals for controlling the capacitance actuator.Type: GrantFiled: May 28, 2003Date of Patent: June 17, 2008Assignee: The United States of America as represented by the Secretary of the NavyInventors: Isaac Lagnado, Paul R. de la Houssaye
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Patent number: 7383071Abstract: One embodiment is a microprobe. An example of the microprobe comprises a housing having an aperture. This example of the microprobe also comprises an ISFET attached to the housing. The ISFET may have a gate located proximate the aperture. This example of the microprobe further comprises a reference electrode attached to the housing proximate the aperture. Another embodiment is a microsensor system. Another embodiment is a method for measuring a characteristic of tissue. Yet another condition embodiment is a method for monitoring tissue pH.Type: GrantFiled: January 20, 2004Date of Patent: June 3, 2008Assignee: United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Paul R. de la Houssaye, Jamie K. Pugh, William Pugh, Dennis E. Amundson, Howard W. Walker
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Patent number: 7297113Abstract: One embodiment is a microprobe. An example of the microprobe comprises a housing having an aperture. This example of the microprobe also comprises an ISFET attached to the housing. The ISFET may have a gate located proximate the aperture. This example of the microprobe further comprises a reference electrode attached to the housing proximate the aperture. Another embodiment is a microsensor system. Another embodiment is a method for measuring a characteristic of tissue. Yet another embodiment is a method for monitoring tissue pH.Type: GrantFiled: June 18, 2004Date of Patent: November 20, 2007Assignee: United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Paul R. de la Houssaye, Jamie K. Pugh, William Pugh, Dennis E. Amundson, Howard W. Walker
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Patent number: 7232699Abstract: A Method of Making a High Precision Microelectromechanical Capacitor with Programmable Voltage Source includes steps for forming a monolithic MEMS device having a capacitance actuator, a trim capacitor, and a high precision, programmable voltage source. The trim capacitor has a variable capacitance value, preferably for making fine adjustments in capacitance. The capacitance actuator is preferably mechanically coupled to and electrically isolated from the trim capacitor and is used to control the capacitance value of the trim capacitor. The capacitance adjustment of the trim capacitor is non-destructive and may be repeated indefinitely. The trim capacitor may be adjusted by mechanically changing the distance between its electrodes. The programmable voltage source provides a highly accurate and stable output voltage potential corresponding to control signals for controlling the capacitance actuator.Type: GrantFiled: March 15, 2005Date of Patent: June 19, 2007Assignee: United States of America as represented by the Secretary of the NavyInventors: Isaac Lagnado, Paul R. de la Houssaye
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Patent number: 6517610Abstract: A microelectromechanical gas concentrator is fabricated for extracting a gaseous component from a gas mixture. The gas concentrator consists of an adsorbent member that alternatively moves between two regions on a single substrate. When the adsorbent member is in the first region, it is allowed to adsorb the gaseous component. When the adsorbent member moves to the second region, it is exposed to radiant energy, causing it to desorb the gaseous component. As the adsorbent member moves alternatively between regions, the gaseous component is adsorbed by the adsorbent member in the first region and desorbed in the second region, resulting in a pumping action that concentrates the gaseous component from one region to the other.Type: GrantFiled: November 13, 2001Date of Patent: February 11, 2003Assignee: The United States of America as represented by the Secretary of the NavyInventor: Paul R. de la Houssaye
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Patent number: 6165801Abstract: A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.Type: GrantFiled: November 18, 1999Date of Patent: December 26, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael J. Burns, Paul R. de la Houssaye, Graham A. Garcia, Stephen D. Russell, Stanley R. Clayton, Andrew T. Barfknecht
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Patent number: 6103540Abstract: A single crystal silicon film nanostructure capable of optical emission is aterally disposed on an insulating transparent substrate of sapphire. By laterally disposing the nanostructure, adequate support for the structure is provided, and the option of fabricating efficient electrical contact structures to the nanostructure is made possible. The method of the invention begins with the deposition of ultrathin layers of silicon on the substrate. A Solid Phase Epitaxy improvement process is then used to remove crystalline defects formed during the deposition. The silicon is then annealed and thinned using thermal oxidation steps to reduce its thickness to be on the order of five nanometers in height. The width and length of the nanostructure are defined by lithography. The nanometer dimensioned silicon is then spin-coated with a resist with width and length definition in the resist being performed by way of electron beam exposure.Type: GrantFiled: November 4, 1998Date of Patent: August 15, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Robert C. Dynes, Paul R. de la Houssaye, Wadad B. Dubbelday, Randy L. Shimabukuro, Andrew S. Katz
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Patent number: 6093941Abstract: A light emitting photonic structure has a transparent substrate, such as sapphire, supporting a layer of group IV semiconductor material, such as silicon, having at least one porous region from which light is emitted as a response to an electrical or optical stimulus. Optionally, the group IV semiconductor material may be germanium, carbon, tin, silicon-germanium, silicon carbide, single crystal structures, polycrystalline structures, or amorphous structures and the transparent substrate may be glass, quartz, fused silica, diamond, ruby, yttria alumina garnet, yttria stabilized zirconium, magnesium fluoride or magnesium oxide. When the stimulus is electrical, the response is electroluminescence or cathodoluminescence and when the stimulus is optical, the response is photoluminescence.Type: GrantFiled: September 9, 1993Date of Patent: July 25, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Wadad B. Dubbelday, Randy L. Shimabukuro, Paul R. de la Houssaye, Diane M. Szaflarski
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Patent number: 6051846Abstract: A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.Type: GrantFiled: April 1, 1993Date of Patent: April 18, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael J. Burns, Paul R. de la Houssaye, Graham A. Garcia, Stephen D. Russell, Stanley R. Clayton, Andrew T. Barfknecht
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Patent number: 5962863Abstract: A single crystal silicon film nanostructure capable of optical emission is laterally disposed on an insulating transparent substrate of sapphire. By laterally disposing the nanostructure, adequate support for the structure is provided, and the option of fabricating efficient electrical contact structures to the nanostructure is made possible. The method of the invention begins with the deposition of ultrathin layers of silicon on the substrate. A Solid Phase Epitaxy improvement process is then used to remove crystalline defects formed during the deposition. The silicon is then annealed and thinned using thermal oxidation steps to reduce its thickness to be on the order of five nanometers in height. The width and length of the nanostructure are defined by lithography. The nanometer dimensioned silicon is then spin-coated with a resist with width and length definition in the resist being performed by way of electron beam exposure.Type: GrantFiled: September 13, 1995Date of Patent: October 5, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Stephen D. Russell, Robert C. Dynes, Paul R. de la Houssaye, Wadad B. Dubbelday, Randy L. Shimabukuro, Andrew S. Katz
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Patent number: 5951757Abstract: A method for fabricating silicon-germanium alloy on a sapphire substrate of the present invention comprises the steps of passivating a surface of a sapphire substrate, maintaining a deposition temperature of about 900 degrees C., exposing the passivated surface to a flow of about 1 slm of about 2 percent silane in a hydrogen carrier and a flow of at least 200 sccm of about 10 percent germane in a hydrogen carrier to form a layer of single crystal silicon germanium alloy on the passivated surface of the sapphire substrate, and ramping the temperature down to about 650 degrees C. during the step of exposing the passivated surface to the germane gas.Type: GrantFiled: May 6, 1997Date of Patent: September 14, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Wadad B. Dubbelday, Paul R. de la Houssaye, Shannon D. Kasa, Isaac Lagnado