Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: Disclosed herein are thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test. In some embodiments, a thermal head comprises a plurality of adapters, one or more heaters, and one or more thermal controllers for independently controlling temperatures of the components. The thermal controllers may control the temperatures of at least some of the components independently such that thermal control of one component does not affect the thermal control of the other component. In some embodiments, the thermal control is by way of one or more cold plates, and the thermal head comprises one or more cold plates. Embodiments of the disclosure further include independent control of one or more forces using one or more force mechanisms.

Abstract: Implantable medical systems enter an exposure mode of operation, either manually via a down linked programming instruction or by automatic detection by the implantable system of exposure to a magnetic disturbance. A controller then determines the appropriate exposure mode by considering various pieces of information including the device type including whether the device has defibrillation capability, pre-exposure mode of therapy including which chambers have been paced, and pre-exposure cardiac activity that is either intrinsic or paced rates. Additional considerations may include determining whether a sensed rate during the exposure mode is physiologic or artificially produced by the magnetic disturbance. When the sensed rate is physiologic, then the controller uses the sensed rate to trigger pacing and otherwise uses asynchronous pacing at a fixed rate.

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. A semiconductor chip with conductive stumps over an active surface, a first layer of encapsulant disposed around the semiconductor chip, over the active surface, and around the conductive stumps, a first conductive layer and first vertical conductive contacts electrically coupled with the conductive stumps, the first conductive layer comprising conductive traces formed over a planarized surface of the encapsulant and conductive stumps, a second layer of encapsulant disposed over the first encapsulant layer, conductive layer, conductive traces, and first vertical conductive contacts, a plurality of conductive pads formed over a planarized surface, and a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.

Abstract: The disclosure concerns electronic assemblies, comprising: a component comprising conductive studs on a surface of the component; a first encapsulant disposed around four side surfaces of the component, over the surface of the component, and around at least a portion of sidewalls of the conductive studs; a conductive backside material disposed over at least a portion of a backside of the component; a substantially planar surface disposed over the surface of the component, wherein the substantially planar surface comprises ends of the conductive studs and a planar surface of the first encapsulant, wherein the planar surface of the first encapsulant comprises a roughness less than 500 nanometers over a characteristic measurement distance; conductive structures disposed over the planar surface and configured to be electrically coupled with the component; a second encapsulant disposed over the conductive structures; and conductive pads disposed over, or within, the second encapsulant for TO interconnection.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: The disclosure concerns method of making a molded substrate, comprising providing a carrier; forming a first conductive layer and first vertical conductive contacts over the carrier; disposing a first layer of encapsulant over the first conductive layer and first vertical conductive contacts; planarizing the first vertical conductive contacts and the first layer of encapsulant to form a first planar surface; forming a second conductive layer and second vertical conductive contacts over the first layer of encapsulant and configured to be electrically coupled with the first conductive layer and first vertical conductive contacts; disposing a second layer of encapsulant over the second conductive layer and second vertical conductive contacts; planarizing the second vertical conductive contacts and the second layer of encapsulant to form a second planar surface; and forming first conductive bumps over the second planar surface, opposite the carrier.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: Disclosed herein are thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test. In some embodiments, a thermal head comprises a plurality of adapters, one or more heaters, and one or more thermal controllers for independently controlling temperatures of the components. The thermal controllers may control the temperatures of at least some of the components independently such that thermal control of one component does not affect the thermal control of the other component. In some embodiments, the thermal control is by way of one or more cold plates, and the thermal head comprises one or more cold plates. Embodiments of the disclosure further include independent control of one or more forces using one or more force mechanisms.

Abstract: Disclosed herein are thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test. In some embodiments, a thermal head comprises a plurality of adapters, one or more heaters, and one or more thermal controllers for independently controlling temperatures of the components. The thermal controllers may control the temperatures of at least some of the components independently such that thermal control of one component does not affect the thermal control of the other component. In some embodiments, the thermal control is by way of one or more cold plates, and the thermal head comprises one or more cold plates. Embodiments of the disclosure further include independent control of one or more forces using one or more force mechanisms.

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.

Abstract: Disclosed herein are thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test. In some embodiments, a thermal head comprises a plurality of adapters, one or more heaters, and one or more thermal controllers for independently controlling temperatures of the components. The thermal controllers may control the temperatures of at least some of the components independently such that thermal control of one component does not affect the thermal control of the other component. In some embodiments, the thermal control is by way of one or more cold plates, and the thermal head comprises one or more cold plates. Embodiments of the disclosure further include independent control of one or more forces using one or more force mechanisms.

Abstract: Disclosed herein are thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test. In some embodiments, a thermal head comprises a plurality of adapters, one or more heaters, and one or more thermal controllers for independently controlling temperatures of the components. The thermal controllers may control the temperatures of at least some of the components independently such that thermal control of one component does not affect the thermal control of the other component. In some embodiments, the thermal control is by way of one or more cold plates, and the thermal head comprises one or more cold plates. Embodiments of the disclosure further include independent control of one or more forces using one or more force mechanisms.

Abstract: A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: A thermally enhanced, chip-scale, Lead-on Chip (“LOC”) semiconductor packages includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: A system for distributing dated promotions over the internet via email to registered consumers permits the consumer to identify goods of interest and offers numerous ways to limit or restrict the number of dated promotions to be received in a given time period, such as by relative importance of goods, level of retail outlet, intended user, and the like, so that received dated promotions are of the most significance to the consumer.

Abstract: A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semi-conductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: There is provided an edge connectable electronic package. The package has a metallic base at least partially coated with a dielectric layer. An interconnection means taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device. The opposing end of the interconnection means extends to the package perimeter for interconnection to a socket or brazing to external leads.

Abstract: There is provided a ball grid array package for housing semiconductor devices. The package has a metallic base with conductive vias extending through holes formed in the base. The conductive vias terminate adjacent an exterior surface of the base. A dielectric coating on at least part of the base and through hole walls electrically isolates the metallic base from the package circuitry.