Patents by Inventor Paul Ruby
Paul Ruby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8971126Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: May 29, 2014Date of Patent: March 3, 2015Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Publication number: 20140293697Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: May 29, 2014Publication date: October 2, 2014Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 8767476Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: April 25, 2011Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 8595422Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.Type: GrantFiled: July 11, 2012Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventors: Paul Ruby, Neal Mielke
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Publication number: 20120275221Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.Type: ApplicationFiled: July 11, 2012Publication date: November 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Paul Ruby, Neal Mielke
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Patent number: 8230158Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.Type: GrantFiled: August 12, 2008Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventors: Paul Ruby, Neal Mielke
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Publication number: 20110199826Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: April 25, 2011Publication date: August 18, 2011Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 7969788Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: August 21, 2007Date of Patent: June 28, 2011Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 7791918Abstract: A method for use with devices in a stacked package is discussed. By preprogramming a unique identifier into a device during manufacture, the device can determine its position in the stack and perform a task based on its position in the stack. In one embodiment, the task is power-up.Type: GrantFiled: September 27, 2007Date of Patent: September 7, 2010Assignee: Intel CorporationInventor: Paul Ruby
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Publication number: 20100039860Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: Micron Technology, Inc.Inventors: Paul Ruby, Neal Mielke
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Patent number: 7535787Abstract: Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.Type: GrantFiled: June 6, 2007Date of Patent: May 19, 2009Inventors: Daniel Elmhurst, Violante Moschiano, Paul Ruby
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Publication number: 20090084838Abstract: A method for use with devices in a stacked package is disclosed. By preprogramming a unique identifier into a device during manufacture, the device can determine its position in the stack and perform a task based on its position in the stack. In one embodiment, the task is power-up.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventor: Paul Ruby
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Publication number: 20090052269Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: August 21, 2007Publication date: February 26, 2009Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Publication number: 20080304327Abstract: Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.Type: ApplicationFiled: June 6, 2007Publication date: December 11, 2008Inventors: Daniel Elmhurst, Violante Moschiano, Paul Ruby
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Patent number: 7193901Abstract: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.Type: GrantFiled: April 13, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Paul Ruby, Sean Eilert
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Publication number: 20060233020Abstract: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.Type: ApplicationFiled: April 13, 2005Publication date: October 19, 2006Inventors: Paul Ruby, Sean Eilert
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Patent number: 5729489Abstract: A method for programming a memory cell having more than two possible states to a desired state. The method includes applying a programming pulse to the memory cell. The change in the amount of charge stored by the memory cell caused by applying the programming pulse to the memory cell is sensed. The control engine determines characterization information indicative of programming characteristics of the memory cell in response to the detected change in the amount of charge stored by the memory cell. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.Type: GrantFiled: December 14, 1995Date of Patent: March 17, 1998Assignee: Intel CorporationInventors: Albert Fazio, Gregory E. Atwood, James O. Mi, Paul Ruby
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Patent number: 5701266Abstract: In a memory device including an array of memory cells, each memory cell having more than two possible states, a method for programming a memory cell to a desired state. The method comprises a control engine programming a subset of the array of memory cells. Characterization information is determined from the step of programming the subset, wherein the characterization information indicates programming characteristics of a representative memory cell of the array of memory cells. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.Type: GrantFiled: December 6, 1996Date of Patent: December 23, 1997Assignee: Intel CorporationInventors: Albert Fazio, Gregory E. Atwood, James O. Mi, Paul Ruby
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Patent number: 5677869Abstract: A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.Type: GrantFiled: December 14, 1995Date of Patent: October 14, 1997Assignee: Intel CorporationInventors: Albert Fazio, Gregory E. Atwood, James Q. Mi, Paul Ruby