Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique.

Abstract: A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n-layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.

Abstract: Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

Abstract: The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.

Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: The present invention provides methods of fabricating floating gate transistors. One method includes forming laterally spaced source and drain regions to define a channel therebetween, forming a first floating gate portion above the channel region, the first floating gate portion extending in a general horizontal direction, forming spacers over the first floating gate portion to define an exposed region on the first floating gate portion, forming a contact coupled to the first floating gate portion at the exposed region, the contact extending vertically above the first portion, forming a second floating gate portion coupled to the contact, the second floating gate portion extending in a general vertical direction, and forming a control gate adjacent to the second portion.

Abstract: An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.

Abstract: The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is located above the transistor and traverses the memory in a direction perpendicular to the control gate.

Abstract: The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.

Abstract: A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory cell also includes a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. The memory cell further includes a second insulating layer formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region. Arrays, memory devices, and systems are further included in the scope of the present invention.