Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

Abstract: In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.

Abstract: The invention relates to a method for reading data with a data burst length (BL) greater than two from a semiconductor memory apparatus, comprising the following steps:

Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.

Abstract: In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

Abstract: A test configuration for a parallel functional testing of semiconductor memory modules includes a test unit which provides a test sequence, feeds it to a module to be tested, and receives response signals generated by the module to be tested after the test sequence has been run through. A test logic circuit, which is connected to the test unit, receives the test sequence and is disposed on the module to be tested. The test unit is connected to the test logic circuit via a narrow interface for a bidirectional communication. For this purpose, the module to be tested has ports for connecting the interface. Only one of the ports serves for outputting of data to be read out from the module. This allows testing a large number of memory modules in parallel.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.