Abstract: A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data.

Abstract: A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Abstract: A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals.

Abstract: A battery monitor with programmable voltage references. The battery monitor includes a comparator circuit connected to a battery for receiving a voltage level thereof and to a voltage reference circuit for receiving a at least one reference voltage generated thereby. A trim circuit is connected to the voltage reference circuit for adjusting the reference voltage(s) and generated by the voltage reference circuit. The comparator circuit compares the voltage level of the battery with the reference voltage(s) generates an output based on the relative value of the battery voltage compared to the reference voltage(s). The trim circuit is programmable and includes a microprocessor connected to a programmable register and a memory. The microprocessor obtains trim data from the memory and writes the trim data to the programmable register.

Abstract: A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.

Abstract: A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier reference signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data.

Abstract: A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardware. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention.

Abstract: A telephone for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The telephone comprises a radio interface connection with the frame formatter, a FIFO/codec interface conductively coupled to the frame formatter, an interrupt interface conductively coupled to the frame formatter, a data control logic interface conductively coupled to the frame formatter, and a microcontroller interface conductively coupled to the frame formatter.

Abstract: A method for enabling communications between a first communications unit and a second communications unit. The first communications unit has a first crystal that provides first unit timing for that unit. The second communications unit has a second crystal that provides second unit timing for the second communications unit. The method includes the steps of receiving the first unit timing by the second communications unit, detecting a transition of a cycle of the first unit timing received, generating a reset pulse upon each detection of the transition of the cycle of the first timing unit received, and initiating a start-up of a new sequence of the second unit timing upon occurrence of the reset pulse. Operation according to the method allows for a wide variety of external protocols to be used with appropriate communications results.

Abstract: A method for generating transmit clock timing of a first communications unit of a communications system. The communications system includes the first communications unit and a second communications unit, each capable of communications with the other. The first communications unit has a first internal clock and the second communications unit has a second internal clock.

Abstract: A time division multiplexed communications system is disclosed. The system includes multiple transceiver pairs. Each of the transceiver pairs operates according to its own timer. The transceiver pairs each include circuitry that synchronizes the respective timers to a common frequency signal supplied to each of the transceiver pairs. By so synchronizing the timer of each transceiver pair to a common frequency signal, transmissions of all the transceiver pairs in the system are synchronized. Synchronization of transmissions can reduce noise and interference between neighboring transceiver pairs.