Abstract: An apparatus and method of keeping an energy storage cell at or above a target temperature, includes receiving at a processing circuit, an analog voltage that is proportional to a temperature of the energy storage cell, converting, at the processing circuit, the analog voltage to a pulse-width-modulated signal having a duty cycle that is proportional to the analog voltage, and driving a switch, with the pulse-width-modulated signal, between conductive and non-conductive states to modulate a voltage passing across (or a current flowing through) a heating element in series with the switch, the heating element being in thermal communication with the energy storage cell, wherein the duty cycle of the pulse-width-modulated signal is adjusted to maintain the temperature of the energy storage cell at or above the target temperature.

Abstract: An apparatus and method for memory backup are disclosed as being operational at a memory module that includes a volatile memory device but which is devoid of a non-volatile memory device. The memory module can emulate operations of a non-volatile memory on the memory module while the memory module is devoid of such non-volatile memory.

Abstract: A peripheral component interconnect express (PCIe) solid state drive (SSD) accelerator, having a PCIe card and separate a flash daughter-card, is provided. By including flash memory devices on a separate daughter-card, the flash memory devices are thermally decoupled from the hotter devices on the main PCIe providing additional thermal operating margins for the entire design. Furthermore, as flash memory devices are the most likely part of the subsystem to wear out over time due, including flash memory devices on a separate daughter-card allows the flash memory devices to become a field replaceable unit that can be easily replaced. EEPROMs may be included on the flash daughter-card to record the current wear state of the NAND flash devices. Knowing the wear history of the flash memory device allows the seller to replace the flash daughter-card of a customer with a daughter-card having a similar wear state.

Abstract: An apparatus and method for memory backup are disclosed as being operational at a memory module that includes a volatile memory device but which is devoid of a non-volatile memory device. The memory module can emulate operations of a non-volatile memory on the memory module while the memory module is devoid of such non-volatile memory.

Abstract: An apparatus and method of keeping an energy storage cell at or above a target temperature, includes receiving at a processing circuit, an analog voltage that is proportional to a temperature of the energy storage cell, converting, at the processing circuit, the analog voltage to a pulse-width-modulated signal having a duty cycle that is proportional to the analog voltage, and driving a switch, with the pulse-width-modulated signal, between conductive and non-conductive states to modulate a voltage passing across (or a current flowing through) a heating element in series with the switch, the heating element being in thermal communication with the energy storage cell, wherein the duty cycle of the pulse-width-modulated signal is adjusted to maintain the temperature of the energy storage cell at or above the target temperature.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: The present disclosure is directed to visual field replacement unit (FRU) identification and retaining FRU status information of one or more field replaceable units in a host system device when one or more of the field replaceable units is removed from the host system device disconnecting host power to the removed field replaceable unit(s). The one or more field replaceable units may be located on a carrier printed circuit board assembly and the host system device may contain multiple field replaceable units and/or multiple carrier printed circuit board subassemblies. Once the host power is disconnected from the carrier, an alternate power source continues to provide power to keep the FRU indicator illuminated for repairs or replacement. The FRU indicator is illuminated long enough for a service technician to place the carrier on a bench or table top and recognize the failed FRU from the remaining FRUs.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).

Abstract: The present disclosure is directed to visual field replacement unit (FRU) identification and retaining FRU status information of one or more field replaceable units in a host system device when one or more of the field replaceable units is removed from the host system device disconnecting host power to the removed field replaceable unit(s). The one or more field replaceable units may be located on a carrier printed circuit board assembly and the host system device may contain multiple field replaceable units and/or multiple carrier printed circuit board subassemblies. Once the host power is disconnected from the carrier, an alternate power source continues to provide power to keep the FRU indicator illuminated for repairs or replacement. The FRU indicator is illuminated long enough for a service technician to place the carrier on a bench or table top and recognize the failed FRU from the remaining FRUs.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).

Abstract: A memory device is provided comprising: a volatile memory device, a non-volatile memory device, a memory control circuit volatile memory controller coupled to the volatile memory device and non-volatile memory device, and a backup power source. The backup power source may be arranged to temporarily power the volatile memory devices and the memory control circuit upon a loss of power from the external power source. Additionally, a switch may serve to selectively couple: (a) a host memory bus to either the volatile memory device or non-volatile memory device; and (b) the volatile memory device to the non-volatile memory device. Upon reestablishment of power by an external power source from a power loss event, the memory control circuit is configured to restore data from the non-volatile memory device to the volatile memory device prior to a host system, to which the memory device is coupled, completes boot-up.

Abstract: Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).

Abstract: A peripheral component interconnect express (PCIe) solid state drive (SSD) accelerator, having a PCIe card and separate a flash daughter-card, is provided. By including flash memory devices on a separate daughter-card, the flash memory devices are thermally decoupled from the hotter devices on the main PCIe providing additional thermal operating margins for the entire design. Furthermore, as flash memory devices are the most likely part of the subsystem to wear out over time due, including flash memory devices on a separate daughter-card allows the flash memory devices to become a field replaceable unit that can be easily replaced. EEPROMs may be included on the flash daughter-card to record the current wear state of the NAND flash devices. Knowing the wear history of the flash memory device allows the seller to replace the flash daughter-card of a customer with a daughter-card having a similar wear state.

Abstract: Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.