Abstract: This invention pertains to a self-aligned, trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects.

Abstract: This invention pertains to a self-aligned trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects.

Abstract: A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.

Abstract: A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.

Abstract: A method for producing field oxide in a silicon substrate by forming a thin oxide layer over the surface of the substrate, forming a thin nitride layer over the thin oxide layer, forming a thick oxide over the thin nitride layer, forming a thick nitride layer over the thick oxide layer; patterning all four of the layers to espose the surface of the substrate where the field oxide is to be formed; and growing the field oxide. Preferably, before the field oxide is grown, trenches are formed into the substrate so that the upper surfaces of the field oxide are substantially planar with the upper surfaces of the substrate. The thin oxide layer minimizes bird beak formation, and eases the removal of the oxide/nitride/oxide/nitride layers. The resultant structure is both planar and bird's beak-free, and is therefore well suited to producing VLSI components having dimensions less than 0.5 microns.