Abstract: A method of error detection in an inkjet printing apparatus having a host coupled to a print head. The method comprises the acts of communicating a first data stream between the host and the print head, inserting a reference data stream into the first data stream, and validating the first data stream based on the reference data stream.

Abstract: Test circuits on heater chips for testing a heater circuit having a heater element and a first power device. The test circuit can include a second power device, a test device configured to hold the first power device off and the second power device on for a selected heater circuit when the test device receives a signal to activate the test circuit, and a common test output to transmit a signal indicative of a state of the selected heater circuit. Methods for using the same are also provided.

Abstract: Test circuits on heater chips for testing a heater circuit having a heater element and a first power device. The test circuit can include a second power device, a test device configured to hold the first power device off and the second power device on for a selected heater circuit when the test device receives a signal to activate the test circuit, and a common test output to transmit a signal indicative of a state of the selected heater circuit. Methods for using the same are also provided.

Abstract: A memory circuit for an inkjet print head having a plurality of memory cells switchably connected to a source and configured in an array, wherein at least one of the memory cells is a reference memory cell and at least one of the remaining cells are data memory cells, and at least one sense amplifier adapted to compare at least one of a current and voltage received from the reference memory cell with at least one of a current and voltage received from one of the data memory cells and generate an output based on the comparison.

Abstract: An improved heater chip for an ink jet print head, the chip including an active heater array and an inactive heater array located adjacent to and extending away from the end of the active heater array. The inactive heater array provides a region adjacent the end of the active heater array that is substantially planar, and also provides a plurality of current paths which reduces energy differences between heater resistors adjacent the end of the active heater array and other heater resistors in the heater array.

Abstract: A circuit compares a difference between first and second voltages to a predetermined voltage. The circuit comprises an amplifier having first and second inputs. First and second capacitors are each coupled at one end to the first input of the amplifier. The first capacitor is charged with the first voltage and subsequently discharged. The second capacitor is charged with a first reference voltage and subsequently discharged. Third and fourth capacitors are each coupled at one end to the second input of the amplifier. The third capacitor is charged with the second voltage and subsequently discharged. The fourth capacitor is charged with a second reference voltage and subsequently discharged.

Abstract: A temperature compensated control circuit includes a load transistor which passes the load current and has an on-resistance which varies with temperature. To provide temperature compensation, first and second pilot transistors are integrated with the load transistor such that as the load transistor heats-up due to the load current passing through the on-resistance of the load transistor, the first and second pilot transistors heat-up due to heat conduction from the load transistor. Each of the pilot transistors has an on-resistance which varies proportionally or similarly to the on-resistance of the load transistor. A first current source supplies a first level of current to the on-resistance of the first pilot transistor to develop a first reference voltage, and a second current source supplies a second level of current to the on-resistance of the second pilot transistor to develop a second reference voltage.

Abstract: A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.