Abstract: A word line driver in a memory block circuit provides reduced propagation delay for a block control signal and higher output drive to the memory cells in a selected row. The block control signal passes through an isolation transistor in response to a first state of a maxi control signal. The block control signal is blocked by the isolation transistor in responsive to a second state of the maxi control signal which reduces capacitive loading on the block control signal and decreases its propagation delay. The combination of the block control signal and the maxi control signal enables a bipolar transistor to generate a high output drive row select signal to activate the memory cells in the selected row.

Abstract: A memory sense amplifier with a latch circuit is provided. The combination of a sense amplifier and a latch circuit allows for increased speed operation and minimum space requirements on an integrated circuit. The memory sense amplifier receives complementary input logic signals that are typically from a memory cell and provides latched complementary output logic signals in response to the voltage levels of the complementary input logic signals.